MC68360CRC25L Freescale Semiconductor, MC68360CRC25L Datasheet - Page 799

• Manufacturer Part Number: MC68360CRC25L
• Description: IC MPU QUICC 25MHZ 241-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360CRC25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 241-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor, Inc.
Applications
QUICC supports internally (e.g., the level of the SIM60 and the level of the CPM). If such a
condition occurs, BERR will be asserted by the QUICC.
9.8.1.9 SOFTWARE WATCHDOG. If desired, the MC68EC030 can program the QUICC
software watchdog to generate a level 7 interrupt or a system reset. In this application, the
software watchdog is configured in software to generate a reset so that the breakpoint logic
can use level 7 interrupts. No additional hardware is required because the connection
between the reset pins of the QUICC and the MC68EC030 is already made.
9.8.1.10 PERIODIC INTERVAL TIMER. If desired, the MC68EC030 can use the periodic
interval timer on the QUICC to generate a system interrupt, such as for a real-time kernel.
No additional hardware is required for this function.
9.8.1.11 MC68EC030 CACHING CONFIGURATION. The MC68EC030 can cache or not
cache data and program memory as desired. However, it is strongly advisable not to cache
the data that is accessed by the QUICC serial channels because of the overhead incurred
every time the cached data area is written.
9.8.1.12 DOUBLE BUS FAULT. In slave mode, the QUICC double bus fault monitor is not
operational.
9.8.1.13 JTAG AND THREE-STATE. The QUICC provides JTAG ports, commonly known
as JTAG. This interface uses five pins: TMS, TDI, TDO, TCK, and TRST. TMS and TDI are
left unconnected because they have internal pullups. The JTAG ports of both parts are dis-
abled in this application; however, the capability could be easily added.
When the QUICC is in master mode, it provides a TRIS pin that allows all outputs on the
device to be three-stated. In slave mode, this feature is not available since the QUICC is a
peripheral of the system.
9.8.1.14 QUICC SERIAL PORTS. The functions on QUICC parallel I/O ports A, B, and C
may be used as desired in this application and have no bearing on the MC68EC030 inter-
face. However, any unused parallel I/O pins should be configured as outputs, so they are
not left floating.
9.8.2 Memory Interfaces
In this application, a number of memory arrays have been developed for EPROM, flash
EPROM, EEPROM, SRAM, and DRAM. Each memory interface can be attached to the sys-
tem bus as desired.
One issue not discussed is the decision of whether external buffers are needed on the sys-
tem bus. This issue depends on the number of memory arrays used in the design and pos-
sibly the layout (i.e., capacitance) of the system bus.
Another issue left to the user is the number of wait states used with each memory system.
This depends on the memory speed, whether external buffers are used, and the loading on
the system bus pins. (The QUICC provides capacitance de-rating figures to calculate the
effect of more or less capacitance on the AC Timing Specifications.)
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MC68360 USER’S MANUAL
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