MC68360CRC25L Freescale Semiconductor, MC68360CRC25L Datasheet - Page 605

• Manufacturer Part Number: MC68360CRC25L
• Description: IC MPU QUICC 25MHZ 241-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360CRC25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 241-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

7.11.7.10 SMC UART ERROR-HANDLING PROCEDURE. The SMC UART reports char-
acter reception error conditions via the channel buffer descriptors, and the SMC UART event
register. There are no transmission errors for the SMC UART controller.
7.11.7.10.1 Overrun Error. The SMC UART maintains a two-character length FIFO for
receiving data (shift register plus data register). The data will be moved to the buffer after
the first character is received into the FIFO. If a receiver FIFO overrun occurs, the channel
writes the received character into the internal FIFO. Then the channel writes the received
character to the buffer, closes the buffer, sets the OV bit in the BD, and generates the RX
interrupt if it is enabled. Reception then continues normally.
7.11.7.10.2 Parity Error. When a parity error occurs, the channel writes the received char-
acter to the buffer, closes the buffer, sets the PR bit in the BD, and generates the RX inter-
rupt if it is enabled. Reception then continues normally.
7.11.7.10.3 Idle Sequence Receive. An idle is detected when one character consisting of
all ones is received. Once an idle is received, the channel counts the number of consecutive
idle characters received. If the count reaches the MAX_IDL value, the buffer is closed, and
an RX interrupt is generated. If no receive buffer is open, this event does not generate an
interrupt or any status information. The idle counter is reset every time a character is
received.
7.11.7.10.4 Framing Error. A framing error is detected by the SMC UART controller when
a character is received with no stop bit. When this error occurs, the channel writes the
received character to the buffer, closes the buffer, sets the FR bit in the BD, and generates
the RX interrupt if it is enabled. When this error occurs, parity is not checked for this char-
acter.
7.11.7.10.5 Break Sequence. A break sequence is detected by the SMC UART receiver
when an all-zero’s character with a framing error is received. When a break sequence is
received, the channel will increment the BRKEC and generate a maskable BRK interrupt in
the SMC UART event register. The channel will also measure the length of the break
sequence and store this value in the BRKLN counter. If the channel was in the middle of
buffer processing when the break was received, the buffer will be closed with the BR bit in
the Rx BD set, and the RX interrupt will be generated if it is enabled.
7.11.7.11 SMC UART MODE REGISTER (SMCMR). The operating mode of an SMC is
defined by the SMCMR. The SMCMR is a 16-bit, memory-mapped, read-write register. The
register is cleared at reset. The function of bits 7–0 is common to each SMC protocol. The
function of bits 15–8 varies according to the protocol selected by the SM bits.
15
—
14
The SMC UART may occasionally get an overrun when the line
is at idle. The user should ignore an overrun error when the line
is known to be at idle.
13
CLEN
12
Freescale Semiconductor, Inc.
11
For More Information On This Product,
SL
10
MC68360 USER’S MANUAL
Go to: www.freescale.com
PEN
9
PM
NOTE
8
7
—
6
Serial Management Controllers (SMCs)
5
SM
4
3
DM
2
TEN
1
REN
0