MC68360CRC25L Freescale Semiconductor, MC68360CRC25L Datasheet - Page 222

• Manufacturer Part Number: MC68360CRC25L
• Description: IC MPU QUICC 25MHZ 241-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360CRC25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 241-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor, Inc.
CPU32+
Result Data:
The “command complete” response ($0FFFF) is returned during the next shift operation.
5.6.2.8.16 Future Commands. Unassigned command opcodes are reserved by Motorola
for future expansion. All unused formats within any revision level will perform a NOP and
return the ILLEGAL command response.
5.6.3 Deterministic Opcode Tracking
The CPU32+ utilizes deterministic opcode tracking to trace program execution. Two signals,
IPIPE and IFETCH, provide all information required to analyze instruction pipeline opera-
tion.
5.6.3.1 INSTRUCTION FETCH (IFETCH). IFETCH indicates which bus cycles are access-
ing data to fill the instruction pipeline. IFETCH is pulse-width modulated to multiplex two indi-
cations on a single pin. Asserted for a single clock cycle, IFETCH indicates that the data
from the current bus cycle is to be routed to the instruction pipeline. IFETCH held low for two
clock cycles indicates that the instruction pipeline has been flushed. The data from the bus
cycle is used to begin filling the empty pipeline. Both user and supervisor mode fetches are
signaled by IFETCH.
Proper tracking of bus cycles via IFETCH on a fast bus requires a simple state machine. On
a two-clock bus, IFETCH may signal a pipeline flush with associated prefetch followed
immediately by a second prefetch. That is, IFETCH remains asserted for three clocks, two
clocks indicating the flush/fetch and a third clock signaling the second fetch. These two oper-
ations are easily discerned if the tracking logic samples IFETCH on the two rising edges of
CLKO1, which follow the AS (DS during show cycles) falling edge. Three-clock and slower
bus cycles allow time for negation of the signal between consecutive indications and do not
experience this operation.
5.6.3.2 INSTRUCTION PIPE (IPIPE1–IPIPE0). The internal instruction pipeline can be
modeled as a three-stage FIFO (see Figure 5-28). Stage A is an input buffer—data can be
used out of stages B and C. The IPIPE1–IPIPE0 signals indicate the advance of instructions
in the pipeline.
The 16-bit instruction register A (IRA) and 16-bit instruction register L (IRL) hold incoming
words as they are prefetched. No decoding occurs in IRA or IRL. Instruction register B (IRB)
provides initial decoding of the opcode and decoding of extension words; it is a source of
immediate data. Instruction register C (IRC) supplies residual opcode decoding during
instruction execution.
IRA is of higher priority than IRL. IRL is only loaded from the IMB when a 32-bit instruction
fetch is performed. IRA is loaded during every instruction fetch.
IRB is loaded from the contents of IRA or IRL, depending on which one is currently valid. If
both IRA and IRL are valid, then IRA is loaded into IRB before IRL is loaded into IRB.
5-80
MC68360 USER’S MANUAL
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