MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 118

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Caches
5-19
back Mode)
(Writethrou
(Writethrou
OPU Read
OPU Read
OPU Write
(Copyback
OPU Write
OPU Write
OPU Write
Operation
Hit (Copy-
Snoop Hit
gh Mode)
gh Mode)
Cache In-
Alternate
validate
Master
Cache
Cache
Mode)
Push
Miss
Miss
Miss
Hit
Hit
(C,W)I1
(C,W)I2 Not possible.
(C,W)I7 Not possible.
(C,W)I5 No action; Remain in cur-
(C,W)I6 No action; Remain in cur-
WI3
WI4
CI3
CI4
Read line from memory
and update cache; Sup-
ply data to OPU; Go to
valid state.
Read line from memory
and update cache; Write
data to cache; Go to dirty
state.
Write data to memory;
Remain in current state.
Not possible.
Not possible.
rent state.
rent state.
Invalid Cases
Table 5-3. Data Cache Line State Transitions
M68060 USER’S MANUAL
(C,W)V1
(C,W)V2 Supply data to OPU; Re-
(C,W)V5 No action; Go to invalid
(C,W)V6 No action; Go to invalid
(C,W)V7 No action; Go to invalid
WV3
WV4
CV3
CV$
Current State
Read new line from mem-
ory and update cache;
supply data to OPU; Re-
main in current state.
main in current state.
Read new line from mem-
ory and update cache;
Write data to cache; Go
to dirty state.
Write data to memory;
Remain in current state.
Write data to cache; Go
to dirty state.
Write data to memory
and to cache; Remain in
current state.
state.
state.
state.
Valid Cases
CD1
CD2 Supply data to OPU; Re-
CD3
CD4 Write data to cache; Re-
CD5 No action (dirty data lost);
CD6
CD7 No action (dirty data lost);
WD
WD
3
4
Push dirty cache line to
push buffer; Read new
line from memory and up-
date cache; Supply data
to OPU; Write push buffer
contents to memory; Go
to valid state.
main in current state.
Push dirty cache line to
push buffer; Read new
line from memory and up-
date cache; Write push
buffer contents to memo-
ry; Remain in current
state.
Write data to memory;
Remain in current state.
main in current state.
Push dirty cache line to
memory; Write data to
memory and to cache;
Go to valid state.
Go to invalid state.
Push dirty cache line to
memory; Go to invalid
state or remain in current
state, depending on the
DPI bit the the CACR.
Go to invalid state.
Dirty Cases
MOTOROLA