MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 215

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Bus Operation
and LOCKE and then relinquishes the bus by asserting BTT. BGR is a qualifier for BG which
indicates to the MC68060 the degree of necessity for relinquishing bus ownership when BG
is negated. BGR primarily affects how the MC68060 behaves during atomic locked
sequences when BG is negated.
The MC68060 arbitration protocol allows bus ownership to be removed from the MC68060
and granted to another bus master with the negation of BG, even if the processor is indicat-
ing a locked sequence is in progress. A LOCK signal is provided by the MC68060 to indicate
the processor intends the current set of bus cycles to be locked together, but this can either
be enforced or overridden by the system bus arbiter’s control of the BGR signal. The asser-
tion of BGR with the negation of BG by an external bus arbiter forces the processor to relin-
quish the bus as soon as the current bus cycle is finished even if the processor is running a
locked sequence of atomic bus cycles. If both BGR and BG are negated when the MC68060
is running a sequence of locked bus cycles, the MC68060 finishes the entire set of atomic
locked bus cycles and then relinquishes the bus at the completion of that unit of atomic
locked bus cycles and no disruption of the atomic sequence occurs. Note the MC68060 may
be running a set of back-to-back atomic locked sequences, the abutment of which an exter-
nal bus arbiter can not detect to determine a safe time to negate BG. With BGR negated the
MC68060 finishes the last bus cycle of the current set of atomic locked bus cycles and then
relinquishes the bus, thus preventing the interruption of that unit of atomic locked sequence
of bus cycles. Figure 7-46 illustrates BGR functionality during locked sequences.
As an alternative to the BGR protocol, the MC68060 retains the LOCKE signal from the
MC68040 bus. The MC68040 uses a LOCKE signal during the last bus cycle of a locked
sequence of bus cycles to allow an external arbiter to detect the boundary between back-to-
back locked sequences on the bus. An external arbiter in a MC68040 system can use the
LOCKE status signal to determine safe times to remove BG without breaking a locked
sequence and allow arbitration to be overlapped with the last transfer in a locked sequence.
However, a retry acknowledge termination during the last bus cycle of a locked sequence
with LOCKE asserted and BG negated requires asynchronous logic in the external bus arbi-
ter to re-assert BG before the bus cycle finishes to prevent the splitting or interruption of the
locked sequence. Use of the BGR protocol prevents this problem by allowing the MC68060
determine the proper time to relinquish bus ownership and simplifies the external bus arbiter
design.
For locked sequences of bus cycles, the MC68060 asserts LOCK with the TS of the first bus
cycle and negates LOCK following the final termination acknowledgment of the last transfer
of the last bus cycle during the execution of the TAS and CAS instructions, on updates of
history information in table searches, and after the execution of MOVEC instructions that set
and later reset the LOCK bit in the BUSCR. Depending on how the arbiter is designed with
respect to LOCK and BGR, this can have the effect of preventing overlapped bus arbitration
during locked sequences. By keeping LOCK asserted throughout the duration of a locked
sequence, the last bus cycle of the sequence can be retried and still maintain the lock status.
7-60
M68060 USER’S MANUAL
MOTOROLA