MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 201

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Bus Operation
7.9 BUS EXCEPTION CONTROL CYCLES
The MC68060 bus architecture requires assertion of TA from an external device to signal
that a bus cycle is complete. TA is not asserted in the following cases:
External circuitry can provide TEA when no device responds by asserting TA within an
appropriate period of time after the processor begins the bus cycle. This allows the cycle to
terminate and the processor to enter exception processing for the error condition. A retry
may be indicated by asserting TEA in combination with TA in the MC68040 acknowledge
termination mode or by asserting TRA if in the native-MC68060 acknowledge termination
mode.
To properly control termination of a bus cycle for a bus error or retry condition, TA and TEA
must be asserted and negated about the same rising edge of BCLK when using the
MC68040 acknowledge termination mode. Table 7-5 lists the control signal combinations
and the resulting bus cycle terminations. Bus error and retry terminations during burst cycles
operate as described in 7.7.2 Line Read Transfer and 7.7.4 Line Write Cycles
7.9.1 Bus Errors
The system hardware can use the TEA signal to abort the current bus cycle when a fault is
detected. A bus error is recognized during a bus cycle when TA is negated and TEA is
asserted (MC68040 acknowledge termination mode) or during a bus cycle when TEA is
asserted (native-MC68060 acknowledge termination mode). Also, for the MC68040
acknowledge termination mode, a retry termination during the 2nd, 3rd, or 4th long word of
a line transfer is interpreted as a bus error termination. This rule applies also for the second,
third, and fourth long-word transfer on a line transfer that was burst inhibited.
7-46
• The external device does not respond.
• No interrupt vector is provided.
• Various other application-dependent errors occur.
NOTES:
Native-MC68060
Native-MC68060 Don’t Care
Acknowledge
Termination
1. A retry termination in MC68040-mode is valid only for the first long word of a line transfer and is considered a
2. A retry termination in native-MC68060-mode is valid only for the first long word of a line transfer it is ignored
MC68040
MC68040
MC68040
bus error termination otherwise. Note that for burst-inhibited line transfers, the resulting long-word bus cycles
are considered part of the original line transfer and would therefore cause a bus error termination as well.
otherwise. Note that for burst-inhibited line transfers, the resulting long-word bus cycles are considered part of
the original line transfer and would therefore ignore the retry termination as well.
Mode
Either
Either
1
2
Don’t Care
Don’t Care Don’t Care
High
High
Low
Low
TA
Table 7-5. Termination Result Summary
TEA
High
High
High
Low
Low
Low
M68060 USER’S MANUAL
Don’t Care
TRA
High
High
High
High
Low
Low
Bus Error—Terminate and Take Bus Error Exception,
Possibly Deferred
Retry Operation—Terminate and Retry
Normal Cycle Terminate and Continue
Insert Wait States
Illegal operation, Not Supported
Result
MOTOROLA