MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 333

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

11.2.1.2 INPUT SIGNALS DURING POWER-UP REQUIREMENT. The
involves the requirement that during power-up, input signals to the MC68060 not exceed V
by more than 4 V. This is achieved by ensuring that the 5-V supply not exceed the 3.3-V
supply by more than 4 V. In any of the previously discussed DC-to-DC conversion solutions,
it is possible to add three diodes in series from the 5-V supply to the 3.3-V plane. During
power-up, the diodes forward bias and thus provide a current path between the 5-V source
and the 3.3-V plane. This solution provides no more than (0.7 * 3) = 2.1 V drop between the
5-V input and the 3.3-V plane. When the voltage regulator stabilizes, the difference of (5 –
3.3) = 1.7 V is insufficient to forward bias the three diodes, hence not dissipating any energy.
Both Motorola and Linear Technologies have indicated that the three diode shunt does not
adversely affect operation.
Figure 11-1, Figure 11-2, and Figure 11-3 include the shunt diodes as proposed to keep the
5-V supply from drifting more than 2.5 V from the 3.3-V plane.
11.2.2 Output Hold Time Differences
On the MC68040, outputs are driven off the falling edge of PCLK. Since the MC68060 drives
everything off the rising edge of CLK, a hold time differential exists and is discussed in the
following paragraphs.
The data write hold time specification may be met by using the extra data hold time mode
to extend the hold time by a full CLK cycle in which CLKEN is asserted. However, using this
mode requires that the IPLx signals be modified to invoke configuration of this mode at reset.
Decreasing the address hold time affects primarily systems containing slow peripherals. An
example of this problem can be shown on a system that does a read of the MC68681 duart
peripheral. If the system design is implemented such that on a read of the MC68681, the
address hold time relative to chip select specification is violated, it is possible to internally
confuse the MC68681 and cause it to enter its test mode. The MC68681 is one of many
devices that require addresses to be stable as long as its chip select is asserted. Figure 11-
5 and Figure 11-6 show the differences between the hold time for the MC68060 the
MC68040.
MOTOROLA
Figure 11-5. MC68040 Address Hold Time
A31–A0
PCLK
BCLK
CSx
TA
TS
M68060 USER’S MANUAL
Applications Information
second
issue
11-11
dd