MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 245

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

with the MOVE to SR or RTE instruction). The level 6 interrupt request and mask level
example in Figure 8-3 is the same as for all interrupt levels except 7.
Note that a mask value of 6 and a mask value of 7 both inhibit request levels of 1–6 from
being recognized. In addition, neither masks an interrupt request level of 7. The only differ-
ence between mask values of 6 and 7 occurs when the interrupt request level is 7 and the
mask value is 7. If the mask value is lowered to 6, a second level 7 interrupt is recognized.
External circuitry can chain or otherwise merge signals from devices at each level, allowing
an unlimited number of devices to interrupt the processor. When several devices are con-
nected to the same interrupt level, each device should hold its interrupt priority level constant
until its corresponding interrupt acknowledge bus cycle ensures that all requests are pro-
cessed. Refer to Section 7 Bus Operation for details on the interrupt acknowledge cycle.
Figure 8-4 illustrates a flowchart for interrupt exception processing. When processing an
interrupt exception, the processor first makes an internal copy of the SR, sets the mode to
supervisor, suppresses tracing, and sets the processor interrupt mask level to the level of
the interrupt being serviced. The processor attempts to obtain a vector number from the
MOTOROLA
IF
IF
IF
IF STILL
IF
IF
IF
IF
IF STILL
EXTERNAL
IPL2–IPL0
001 ($6)
100 ($3)
001 ($6)
001 ($6)
100 ($3)
100 ($3)
000 ($7)
000 ($7)
000 ($7)
000 ($7)
100 ($3)
Figure 8-3. Interrupt Recognition Examples
AND RTE SO THAT
AND RTE SO THAT
AND STILL
AND STILL
AND STILL
AND STILL
AND
AND
AND
M68060 USER’S MANUAL
INTERRUPT PRIORITY
MASK (I2–I0)
101 ($5)
110 ($6)
110 ($6)
101 ($5)
101 ($5)
101 ($5)
101 ($5)
111 ($7)
111 ($7)
111 ($7)
101 ($5)
THEN
THEN
THEN
THEN
THEN
THEN
THEN
THEN
THEN
LEVEL 6 INTERRUPT
NO ACTION
NO ACTION
LEVEL 6 INTERRUPT
LEVEL 7 INTERRUPT
NO ACTION
NO ACTION
LEVEL 7 INTERRUPT (TRANSITION)
LEVEL 7 INTERRUPT (LEVEL COMPARISON)
ACTION
Exception Processing
(INITIAL CONDITIONS)
(INITIAL CONDITIONS)
(LEVEL COMPARISON)
(LEVEL COMPARISON)
(TRANSITION)
8-13