MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 145

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

6.6.3.1 TRAP DISABLED RESULTS (FPCR OPERR BIT CLEARED). For
OUT instruction with the format S, D, or X, an OPERR is impossible. For an FMOVE OUT
instruction with the format B, W, or L, an OPERR is possible only on an integer overflow, if
the source is an infinity, or if the source is a NAN. On the integer overflow and infinity source
cases, the largest positive or negative integer that can fit in the specified destination size (B,
W, or L) is stored. On the NAN source case, the 8, 16, or 32 most significant bits of the NAN
significand is stored in the B, W, or L destination.
For FMOVE OUT with the format P (packed decimal), if the k-factor is greater than +17, the
result returned is a packed decimal string that assumes a k-factor equal to +17. For packed
decimal results where the absolute value of the exponent is greater than 999, the decimal
string is returned with the three least significant exponent digits in EXP2, EXP1, and EXP0.
The fourth digit, EXP3, is supplied in the most significant four bits of the third byte in the
string.
For all other OPERR cases, the destination is a floating-point data register. An extended-
precision non-signaling NAN is stored in the destination.
6.6.3.2 TRAP ENABLED RESULTS (FPCR OPERR BIT SET). For
cases, the destination is written as if the trap were disabled, and then control is passed to
MOTOROLA
FADD
FDIV
FMOVE to B,W,or L
FMUL
FSQRT
FSUB
FACOS
FASIN
FATANH
FCOS
FGETEXP
FGETMAN
FLOG10
FLOG2
FLOGN
FLOGNP1
FMOD
FMOVE to P
FREM
FSCALE
FSGLDIV
FSGLMUL
FSIN
FSINCOS
FTAN
Instruction
Table 6-12. Possible Operand Errors Exceptions
[(+ ) + (– )] or [(– ) + (+ )]
(0
Integer overflow, source is nonsignaling NAN or
One operand is 0 and other is +
(Source < 0) or (
[(+ ) – (+ )] or [(– ) – (– )]
Source is
Source is
Source is
Source is
Source is
Source is
Source is < 0 or
Source is < 0 or
Source is < 0 or
Source is
Floating-point data register is
Source exponent > 999 (decimal) or k-factor > 17
Floating-point data register is
Source is
(0
One operand is 0, other operand is
Source is
Source is
Source is
0) or (
0) or(
M68060 USER’S MANUAL
1 or
, > +1, or < –1
, > +1, or < –1
, > +1, or < –1
, other operand not a NAN
Non-Native to MC68060
)
Native to MC68060
Condition Causing Operand Error
or source is 0, other operand is not a NAN
or source is 0, other operand is not a NAN
the
Floating-Point Unit
FMOVE
an
FMOVE
OUT
6-27