MPC8321CVRADDC Freescale Semiconductor, MPC8321CVRADDC Datasheet - Page 11

• Manufacturer Part Number: MPC8321CVRADDC
• Description: IC MPU PWRQUICC II 516-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8321CVRADDC

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 266MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 516-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8323E-MDS-PB
• Maximum Clock Frequency: 266 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 16 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Cpu Speed: 266MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 516
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.2
The primary clock source for the MPC8323E can be one of two inputs, CLKIN or PCI_CLK, depending
on whether the device is configured in PCI host or PCI agent mode.
(CLKIN/PCI_CLK) AC timing specifications for the MPC8323E.
5
This section describes the AC electrical specifications for the reset initialization timing requirements of
the MPC8323E.
component(s).
Freescale Semiconductor
CLKIN input current
PCI_SYNC_IN input current
PCI_SYNC_IN input current
CLKIN/PCI_CLK frequency
CLKIN/PCI_CLK cycle time
CLKIN rise and fall time
PCI_CLK rise and fall time
CLKIN/PCI_CLK duty cycle
CLKIN/PCI_CLK jitter
Notes:
1. Caution: The system, core, security, and QUICC Engine block must not exceed their respective maximum or minimum
2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low to
Required assertion time of HRESET or SRESET (input) to activate reset
flow
Required assertion time of PORESET with stable clock applied to CLKIN
when the MPC8323E is in PCI host mode
Required assertion time of PORESET with stable clock applied to
PCI_SYNC_IN when the MPC8323E is in PCI agent mode
operating frequencies.
allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
RESET Initialization
AC Electrical Characteristics
Parameter/Condition
Table 9
Parameter/Condition
Table 7. CLKIN DC Electrical Characteristics (continued)
provides the reset initialization AC timing specifications for the reset
Table 9. RESET Initialization Timing Specifications
OV
0.5 V ≤ V
Table 8. CLKIN AC Timing Specifications
DD
0 V ≤ V
0 V ≤ V
– 0.5 V ≤ V
IN
IN
≤ OV
IN
≤ 0.5 V or
t
≤ OV
t
KHK
PCH
Symbol
t
DD
KH
f
t
IN
CLKIN
CLKIN
/t
—
, t
, t
DD
≤ OV
– 0.5 V
CLKIN
KL
PCL
DD
Min
0.6
0.6
25
15
40
—
I
I
I
IN
IN
IN
Min
32
32
32
Typical
Table 8
0.8
0.8
—
—
—
—
—
—
—
Max
provides the clock input
—
—
—
66.67
±150
Max
1.2
60
—
4
t
t
PCI_SYNC_IN
PCI_SYNC_IN
t
CLKIN
Unit
±50
±5
±5
RESET Initialization
MHz
Unit
ns
ns
ns
ps
%
Notes
Notes
4, 5
μA
μA
μA
—
1
2
2
3
1
2
1
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