MPC8321CVRADDC Freescale Semiconductor, MPC8321CVRADDC Datasheet - Page 66

• Manufacturer Part Number: MPC8321CVRADDC
• Description: IC MPU PWRQUICC II 516-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8321CVRADDC

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 266MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 516-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8323E-MDS-PB
• Maximum Clock Frequency: 266 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 16 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Cpu Speed: 266MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 516
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Clocking
The ce_clk frequency is determined by the QUICC Engine PLL multiplication factor (RCWL[CEPMF)
and the QUICC Engine PLL division factor (RCWL[CEPDF]) according to the following equation:
When CLKIN is the primary input clock,
When PCI_CLK is the primary input clock,
See the “QUICC Engine PLL Multiplication Factor” section and the “QUICC Engine PLL Division
Factor” section in the MPC8323E PowerQUICC II Pro Communications Processor Reference Manual for
more information.
The DDR SDRAM memory controller operates with a frequency equal to twice the frequency of csb_clk.
Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider
(÷2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate
is the same frequency as ddr_clk.
The local bus memory controller operates with a frequency equal to the frequency of csb_clk. Note that
lbc_clk is not the external local bus frequency; lbc_clk passes through the LBC clock divider to create the
external local bus clock outputs (LSYNC_OUT and LCLK[0:2]). The LBC clock divider ratio is
controlled by LCRR[CLKDIV]. See the “LBC Bus Clock and Clock Ratios” section in the MPC8323E
PowerQUICC II Pro Communications Processor Reference Manual for more information.
In addition, some of the internal units may be required to be shut off or operate at lower frequency than
the csb_clk frequency. These units have a default clock ratio that can be configured by a memory mapped
register after the device comes out of reset.
frequency. Refer to the “System Clock Control Register (SCCR)” section in the MPC8323E PowerQUICC
II Pro Communications Processor Reference Manual for a detailed description.
Table 57
conditions (see
66
Security core, I2C, SAP, TPR
PCI and DMA complex
e300 core frequency ( core_clk )
Coherent system bus frequency ( csb_clk )
QUICC Engine frequency ( ce_clk )
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
provides the operating frequencies for the 8323E PBGA under recommended operating
ce_clk = (primary clock input × CEPMF) ÷ (1 + CEPDF)
ce_clk = [primary clock input × CEPMF × (1 + ~CFG_CLKIN_DIV)] ÷ (1 + CEPDF)
Setting the clock ratio of these units must be performed prior to any access
to them.
Table
Unit
2).
Characteristic
Table 57. Operating Frequencies for PBGA
Table 56. Configurable Clock Units
1
Default Frequency
Table 56
csb_clk
csb_clk
NOTE
specifies which units have a configurable clock
Off, csb_clk /2, csb_clk /3
Off, csb_clk
Max Operating Frequency
Options
333
133
200
Freescale Semiconductor
MHz
MHz
MHz
Unit