MPC8321CVRADDC Freescale Semiconductor, MPC8321CVRADDC Datasheet - Page 54

• Manufacturer Part Number: MPC8321CVRADDC
• Description: IC MPU PWRQUICC II 516-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8321CVRADDC

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 266MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 516-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8323E-MDS-PB
• Maximum Clock Frequency: 266 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 16 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Cpu Speed: 266MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 516
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Package and Pin Listings
54
LCS1
LCS2
LCS3
LWE0
LWE1
LBCTL
LALE
CFG_RESET_SOURCE[0]/LSDA10/LGPL0
CFG_RESET_SOURCE[1]/LSDWE/LGPL1
LSDRAS/LGPL2/LOE
CFG_RESET_SOURCE[2]/LSDCAS/LGPL3
LGPL4/LGTA/LUPWAIT/LPBSE
LGPL5
LCLK0
LCLK1
UART_SOUT1/MSRCID0 (DDR ID)/LSRCID0
UART_SIN1/MSRCID1 (DDR ID)/LSRCID1
UART_CTS1/MSRCID2 (DDR ID)/LSRCID2
UART_RTS1/MSRCID3 (DDR ID)/LSRCID3
UART_SOUT2/MSRCID4 (DDR ID)/LSRCID4
UART_SIN2/MDVAL (DDR ID)/LDVAL
UART_CTS2
UART_RTS2
IIC_SDA/CKSTOP_OUT
IIC_SCL/CKSTOP_IN
MCP_OUT
IRQ0/MCP_IN
IRQ1
IRQ2
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
Signal
Table 55. MPC8323E PBGA Pinout Listing (continued)
Programmable Interrupt Controller
I
2
C interface
DUART
Package Pin Number
AB25
AA23
AA24
AC22
AE24
AF24
AD25
AD26
W25
G23
Y23
V25
V24
K23
H23
Y24
Y25
L23
J23
G1
G2
H3
K3
H2
H1
K4
K1
K2
J3
Pin Type
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
O
O
O
O
O
O
O
O
O
O
O
I
I
Freescale Semiconductor
Supply
Power
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
Notes
4, 8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
4
4
4
4
4
7
4
4
7
7
2
2