MPC8321CVRADDC Freescale Semiconductor, MPC8321CVRADDC Datasheet - Page 69

• Manufacturer Part Number: MPC8321CVRADDC
• Description: IC MPU PWRQUICC II 516-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8321CVRADDC

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 266MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 516-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8323E-MDS-PB
• Maximum Clock Frequency: 266 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 16 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Cpu Speed: 266MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 516
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22.5
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk).
in
Freescale Semiconductor
Table 60
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
Core PLL Configuration
should be considered reserved.
VCO divider (RCWL[COREPLL[0:1]]) must be set properly so that the
core VCO frequency is in the range of 500–800 MHz.
0-1
nn
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
Table 60
RCWL[COREPLL]
Core VCO frequency = core frequency × VCO divider
0000
0001
0001
0001
0001
0001
0001
0001
0001
0010
0010
0010
0010
0010
0010
0010
0010
0011
0011
0011
0011
2-5
shows the encodings for RCWL[COREPLL]. COREPLL values not listed
Table 60. e300 Core PLL Configuration
6
n
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
core_clk : csb_clk Ratio
(PLL off, csb_clk clocks
PLL bypassed
core directly)
NOTE
1.5:1
1.5:1
1.5:1
1.5:1
2.5:1
2.5:1
2.5:1
2.5:1
1:1
1:1
1:1
1:1
2:1
2:1
2:1
2:1
3:1
3:1
3:1
3:1
(PLL off, csb_clk clocks
PLL bypassed
VCO Divider
core directly)
÷2
÷4
÷8
÷8
÷2
÷4
÷8
÷8
÷2
÷4
÷8
÷8
÷2
÷4
÷8
÷8
÷2
÷4
÷8
÷8
Clocking
69