DP83905AVQB National Semiconductor, DP83905AVQB Datasheet - Page 10

• Manufacturer Part Number: DP83905AVQB
• Description: IC CONTROLR AT/LAN TP IN 160PQFP
• Manufacturer: National Semiconductor
• Series: AT/LANTIC™r

Specifications of DP83905AVQB

• Controller Type: AT, LAN Twisted-Pair Interface Controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 100mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP83905AVQB

4 0 Functional Description
Shared Memory Compatible Mode I O Address
Mapping
The shared memory is at an address decided by the Ad-
dress Decode Register and the base I O address of
AT LANTIC Controller is configured in Configuration Regis-
ter A At that address the following structure appears
The AT Detect Register indicates whether AT LANTIC Con-
troller is in an 8- or 16-bit slot The least significant bit of this
register is set high when AT LANTIC Controller is in 16-bit
mode and low in 8-bit mode Addresses 08H to 10H are
Addr
0A
0B
0C
0D
0E
FIGURE 3 Shared Memory Mode a) Register
00
01
02
03
04
05
06
07
08
09
0F
10
1F
to
Mapping and b) NIC Core Memory Map
FFFFH
C000H
0000H
4000H
8000H
Node addr 0
Node addr 1
Node addr 2
Node addr 3
Node addr 4
Node addr 5
Checksum
AT detect
Control 1
Control 2
registers
Unused
Unused
Unused
Unused
Unused
D7–0
05h
NIC
D15
(a)
(b)
Buffer RAM
Buffer RAM
Buffer RAM
Buffer RAM
Aliased
Aliased
Aliased
8k x 16
(Read only)
(Read only)
(Read only)
(Read only)
(Read only)
(Read only)
(Read only)
(Read only)
(Read only)
(Continued)
D0
10
specified as the PROM space for compatibility with the Eth-
ercard PLUS16 This is actually an array of 8-bit registers
which are loaded from an external EEPROM after
AT LANTIC Controller is initialized by a reset pulse The
user should program the EEPROM to contain these values
The 8k words of memory can be accessed directly by the
host system in the same manner as any other memory Typ-
ically the programmer would remove data from this buffer
using a ‘‘MOV’’ or ‘‘MOVSW’’ instruction
8-BIT SHARED MEMORY COMPATIBLE MODE
In this mode the I O map remains the same The NIC core
can still operate in 16-bit mode if bit 6 of Control Register 2
is set high and the full 16 kbytes of RAM are still available
However only 8-bit system accesses are allowed If bit 6 of
Control register 2 is low the NIC core must operate in 8-bit
mode and only 8k of memory is available The NIC Core
data width is set by the WTS bit in the Data Configuration
Register
A low cost card using only one 8 kbyte RAM can be de-
signed If the DWlD pin is left unconnected or tied to GND
then the AT LANTIC Controller will always operate in 8-bit
mode regardless of the slot the board is in
If DWID is low the address bits of Control Register 2 should
not be written to as they have no effect In this mode the
address comparator assumes that SA19 is to be compared
to a logic high with the other address comparisons pro-
grammed into Control Register 1
SHARED MEMORY NON-COMPATIBLE MODE
These modes are similar to the compatible mode The dif-
ference is that they map a full 64 kbytes of RAM into the
PC’s memory address space The I O map remains the
same
I O PORT ARCHITECTURE
This is the architecture used by Novell’s NE2000 In this
mode the AT LANTIC Controller’s internal memory map is
accessed byte or word at a time via a port within the sys-
tem’s I O space AT LANTIC Controller is programmed by
the user to control the transfers between its internal memo-
ry and the I O port
In this mode the AT LANTIC Controller’s internal registers
and the memory access port are accessed within the sys-
tem’s I O map The address within this I O map is set by
Configuration Register A
FIGURE 4 I O Port
TL F 11498 – 6