DP83905AVQB National Semiconductor, DP83905AVQB Datasheet - Page 33

• Manufacturer Part Number: DP83905AVQB
• Description: IC CONTROLR AT/LAN TP IN 160PQFP
• Manufacturer: National Semiconductor
• Series: AT/LANTIC™r

Specifications of DP83905AVQB

• Controller Type: AT, LAN Twisted-Pair Interface Controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 100mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP83905AVQB

D3–D5
D6 D7
5 0 Register Descriptions
COMMAND REGISTER (CR) 00H (READ WRITE)
The Command Register is used to initiate transmissions enable or disable Remote DMA operations and to select register
pages To issue a command the microprocessor sets the corresponding bit(s) (RD2 RDl RD0 TXP) Further commands may be
overlapped but with the following rules (1) If a transmit command overlaps with a remote DMA operation bits RD0 RD1 and
RD2 must be maintained for the remote DMA command when setting the TXP bit Note if a remote DMA command is re-issued
when giving the transmit command the DMA will complete immediately if the remote byte count register has not been re-initial-
ized (2) If a remote DMA operation overlaps a transmission RD0 RD1 and RD2 may be written with the desired values and a
‘‘0’’ written to the TXP bit Writing a ‘‘0’’ to this bit has no effect (3) A remote write DMA may not overlap remote read operation
or visa versa Either of these operations must either complete or be aborted before the other operation may start Bits PS1 PS0
RD2 and STP may be set any time
Bits
Note 1 If a remote DMA operation is aborted and the remote byte count has not decremented to zero the data transfer port should be read for a remote read or
send packet or written to for a remote write This is required to ensure future correct operation
D0
D1
D2
STP
STA
TXP
RD0–RD2
PS0 PS1
Symbols
PS1
STOP Software reset command takes the controller offline no packets will be received or
transmitted Any reception or transmission in progress will continue to completion before entering
the reset state To exit this state the STP bit must be reset and the STA bit must be set high To
perform a software reset this bit should be set high The software reset has executed only when
indicated by the RST bit in the ISR being set to at 1 STP powers up high
Note If the AT LANTIC Controller has previously been in start mode and the STP is set both the STP and STA bits will remain set
START This bit is used to activate the NIC Core after either power up or when the NIC Core has
been placed in a reset mode by software command or error STA powers up low
TRANSMIT PACKET This bit must be set to initiate transmission of a packet TXP is internally
reset either after the transmission is completed or aborted This bit should be set only after the
Transmit Byte Count and Transmit Page Start registers have been programmed
REMOTE DMA COMMAND These three encoded bits control operation of the Remote DMA
channel RD2 can be set to abort any Remote DMA command in progress The Remote Byte Count
Registers should be cleared when a Remote DMA has been aborted The Remote Start Addresses
are not restored to the starting address if the Remote DMA is aborted
RD2
PAGE SELECT These two encoded bits select which register page is to be accessed with
addresses RA0–3
PS1
7
0
0
0
0
1
0
0
1
1
PS0
RD1
PS0
6
0
0
1
1
X
0
1
0
1
(Continued)
RD2
Register Page 0
Register Page 1
Register Page 2
Reserved
5
RD0
X
0
1
0
1
RD1
4
33
RD0
Not Allowed
Remote Read
Remote Write
Send Packet
Abort Complete Remote DMA (Note 1)
3
Description
TXP
2
STA
1
STP
0