DP83905AVQB National Semiconductor, DP83905AVQB Datasheet - Page 63

IC CONTROLR AT/LAN TP IN 160PQFP

DP83905AVQB

Manufacturer Part Number
DP83905AVQB
Description
IC CONTROLR AT/LAN TP IN 160PQFP
Manufacturer
National Semiconductor
Series
AT/LANTIC™r
Datasheet

Specifications of DP83905AVQB

Controller Type
AT, LAN Twisted-Pair Interface Controller
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
100mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
160-BFQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Interface
-
Other names
*DP83905AVQB

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6 0 Operation of AT LANTIC Controller
(Continued)
16-Bit Shared Memory Mode Write Bus Timing with DWID High
TL F 11498 – 46
This is the type of cycle used to write 16 bits to buffer RAM in shared memory mode when DWID is high These accesses are
entirely asynchronous with the AT LANTIC Controller responding when it decodes the correct address on LA17– 23 SA0 – 19
and a MWR If AEN is high the cycle will be ignored CHRDY is deasserted if the AT LANTIC Controller is not ready to respond
and asserted when ready If it is ready immediately CHRDY is not deasserted The 8 16-bit in Control Register 2 must be set to
allow generation of M16 This will be generated whenever the LA17 – 23 lines match the corresponding values in Control
Register 2 It will therefore be generated for a full 128 kbytes of address space although the AT LANTIC Controller will occupy
less than that It may be preferable to only set the 8 16-bit for the duration of a transfer to the buffer RAM The AT LANTIC
Controller will also compare the address line programmed in Control Register 1 before allowing accesses to buffer RAM and
therefore do a complete decode The system indicates that this is a 16-bit transfer by asserting SBHE and accessing an even
address SA0 low The full 16 bits of data bus are used on both system and memory support busses
63

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