DP83905AVQB National Semiconductor, DP83905AVQB Datasheet - Page 5

• Manufacturer Part Number: DP83905AVQB
• Description: IC CONTROLR AT/LAN TP IN 160PQFP
• Manufacturer: National Semiconductor
• Series: AT/LANTIC™r

Specifications of DP83905AVQB

• Controller Type: AT, LAN Twisted-Pair Interface Controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 100mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP83905AVQB

ISA BUS INTERFACE PINS (Continued)
NETWORK INTERFACE PINS
123
122
89–92
61
93
156–153
150 151
141
142
145
146
147
148
5
4
3
1
2
Pin No
2 0 Pin Description
Attachment Unit Interface TPI
Driver Types are I
CHRDY
AEN
INT0–3
DWID
lSACLK
TXOd
TXO
RXI
TX
TX
RX
RX
CD
CD
TXLED
RXLED
COLED
GDLNK
POLED
b
a
b
Pin Name
a
b
a
a
a
e
a
RXI
Input O
TXOd
TXO
b
e
b
b
e
Twisted Pair Interface LED
Output I O
Type
(Continued)
MOS
OCH
3SH
LED
LED
LED
LED
LED
TTL
TTL
AUI
AUI
AUI
TPI
TPI
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
e
Bi-directional Output OCH
CHANNEL READY This signal is used to insert wait states into system accesses
DMA ACTIVE This signal indicates that the system’s DMA controller has control
of the bus
INTERRUPT REQUEST The operation of these 4 outputs is determined by the
Configuration registers They can either be used to directly drive the interrupt lines
or used as a 3-bit code with a strobe to generate up to 8 interrupts
DATA WIDTH This input specifies whether the AT LANTIC Controller is
interfacing to an 8- or 16-bit ISA bus When high it is in 16-bit mode It has an
internal pull-down resistor
ISA CLOCK Clock from ISA bus This signal is only required if CHRDY timing has
to be altered by changing the CHRDY bit of Configuration Register B
TWISTED PAIR TRANSMIT OUTPUTS These high drive CMOS level outputs
are resistively combined external to the chip to produce a differential output signal
with equalization to compensate for Intersymbol Interference (lSI) on the twisted
pair medium
TWISTED PAIR RECEIVE INPUTS These inputs feed a differential amplifier
which passes valid data to the ENDEC module
AUI TRANSMIT OUTPUT Differential driver which sends the encoded data to the
transceiver The outputs are source followers which require 270
resistors
AUI RECEIVE INPUT Differential receive input pair from the transceiver
AUI COLLISION INPUT Differential collision pair input from the transceiver
TRANSMIT An open-drain active Iow output It is asserted for approximately
50 ms whenever the AT LANTIC Controller transmits data in either AUI or TPI
modes
RECEIVE An open-drain active low output It is asserted for approximately 50 ms
whenever receive data is detected in either AUI or TPI mode
COLLISION An open-drain active Iow output It is asserted for approximately 50
ms whenever the AT LANTIC Controller detects a collision in either AUI or TPI
modes
GOOD LINK An open-drain active low output This pin operates as an output to
display link integrity status if this function has not been disabled by the GDLNK bit
in Configuration Register B
POLARITY An open-drain active low output This signal is normally inactive
When the TPI module detects seven consecutive link pulses or three consecutive
received packets with reversed polarity POLED is asserted
This output is off if the AT LANTIC Controller is in AUI mode or if link testing is
enabled and the link integrity is bad (i e the twisted pair link has been broken)
This output is on if the AT LANTIC Controller is in Twisted Pair Interface (TPI)
mode link integrity checking is enabled and the link integrity is good (i e the
twisted pair link has not been broken) or if the link testing is disabled
e
LED Drive MOS
e
5
Open Collector 3SH
e
CMOS Level Compatible XTAL
Description
e
TRI-STATE Output TTL
e
Crystal
e
TTL Compatible AUI
pull-down
e