DP83905AVQB National Semiconductor, DP83905AVQB Datasheet - Page 24

• Manufacturer Part Number: DP83905AVQB
• Description: IC CONTROLR AT/LAN TP IN 160PQFP
• Manufacturer: National Semiconductor
• Series: AT/LANTIC™r

Specifications of DP83905AVQB

• Controller Type: AT, LAN Twisted-Pair Interface Controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 100mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP83905AVQB

4 0 Functional Description
clock signals and data The differential input must be exter-
nally terminated with two 39
if the standard 78
Ethernet applications these resistors are optional To pre-
vent noise from falsely triggering the decoder a squelch
circuit at the input rejects signals with levels less than
The AT LANTIC Controller may tolerate bit jitter up to 20 ns
in the received data The decoder detects the end of a
frame when no more mid-bit transitions are detected
Collision Translator
When in AUI Mode the Ethernet transceiver (DP8392 CTl)
detects a collision it generates a 10 MHz signal to the dif-
ferential collision inputs (CD
ler When these inputs are detected active the AT LANTIC
Controller uses this signal to back off its current transmis-
sion and reschedule another one
In this mode the COLED output will indicate when the CD
lines are active during activity on the network This means it
will correctly indicate any collision on the network but will
not be lit for heartbeat or if there is no cable connected
The collision differential inputs are terminated the same way
as the differential receive inputs The squelch circuitry is
also similar rejecting pulse levels less than
PLL V
The PLL V
lock loop (PLL) of the ST-NIC ENDEC unit Since this is an
b
175 mV Data becomes valid typically within 6 bit times
CC
Power Supply Consideration
CC
pin is the
FIGURE 21 Connection from AT LANTIC Controller’s AUI Port to the AUI Connector
transceiver drop cable is used in thin
a
5V power supply for the phase
g
) of the AT LANTIC Control-
resistors connected in series
b
(Continued)
175 mV
g
24
analog circuit excessive noise on the PLL V
fect the performance of the PLL This noise if in the
10 kHz– 400 kHz range can reduce the jitter performance of
the ENDEC resulting in missing packets or CRC errors
If the power supply noise is causing significant packet re-
ception error a low pass filter could be added to reduce the
power supply noise and hence improve the jitter perform-
ance Standard analog design techniques should be utilized
when laying out the power supply traces on the board If the
digital power supply is used it may be desirable to add a
one pole RC filter (designed to have a cut-off frequency of
1 kHz) as shown in Figure 4 to improve the jitter perform-
ance The PLL V
across the resister is less than 90 mV which will not affect
the PLL’s operation
FIGURE 22 Filtering Power Supply Noise
CC
only draws 3 mA– 4 mA so the voltage
CC
TL F 11498 – 19
TL F 11498 – 18
pin can af-