DP83905AVQB National Semiconductor, DP83905AVQB Datasheet - Page 67

• Manufacturer Part Number: DP83905AVQB
• Description: IC CONTROLR AT/LAN TP IN 160PQFP
• Manufacturer: National Semiconductor
• Series: AT/LANTIC™r

Specifications of DP83905AVQB

• Controller Type: AT, LAN Twisted-Pair Interface Controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 100mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP83905AVQB

6 0 Operation of AT LANTIC Controller
(Continued)
Boot PROM Write Bus Timing
TL F 11498 – 50
This is the type of cycle used to write to the boot PROM These accesses are entirely asynchronous with the AT LANTIC
Controller responding when it decodes the correct address on SA0– 19 and a SMWR If AEN is high the cycle will be ignored
CHRDY is deasserted if the AT LANTIC Controller is not ready to respond and asserted when ready If it is ready immediately
CHRDY is not deasserted M16 is only generated if the AT LANTIC Controller is 1) in shared memory mode AND 2) DWID
is high AND 3) 8 16-bit in Control Register 2 is high AND 4) the LA17– 23 lines match the corresponding values in
Control Register 2 The data will normally be taken from SD0– 7 However if M16 is generated and the access is to an odd
address the data will be taken from SD8–15 The data will always be driven onto MSD0– 7 The BPWR bit of Configuration
Register B must be high to allow write cycles to the boot PROM
67