DP83849CVS/NOPB National Semiconductor, DP83849CVS/NOPB Datasheet - Page 42

• Manufacturer Part Number: DP83849CVS/NOPB
• Description: IC TXRX ETHERNET PHY DUAL 80TQFP
• Manufacturer: National Semiconductor
• Type: Transceiverr

Specifications of DP83849CVS/NOPB

• Number Of Drivers/receivers: 2/2
• Protocol: Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP, 80-VQFP
• Data Rate: 100Mbps
• Supply Voltage Range: 3V To 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 80
• Operating Temperature Range: 0°C To +70°C
• Msl: MSL 3 - 168 Hours
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Data Rate Max: 10Mbps
• For Use With: DP83849CVS-EVK - BOARD EVALUATION DP83849CVS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DP83849CVS; *DP83849CVS/NOPB; DP83849CVS

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6.0 Reset Operation
The DP83849C includes an internal power-on reset (POR)
function and does not need to be explicitly reset for normal
operation after power up. If required during normal opera-
tion, the device can be reset by a hardware or software
reset.
6.1 Hardware Reset
A hardware reset is accomplished by applying a low pulse
(TTL level), with a duration of at least 1
RESET_N pin. This will reset the device such that all regis-
ters will be reinitialized to default values and the hardware
configuration values will be re-latched into the device (simi-
lar to the power-up/reset operation).
6.2 Full Software Reset
A full-chip software reset is accomplished by setting the
reset bit (bit 15) of the Basic Mode Control Register
s, to the
42
(BMCR). The period from the point in time when the reset
bit is set to the point in time when software reset has con-
cluded is approximately 1 s.
The software reset will reset the device such that all regis-
ters will be reset to default values and the hardware config-
uration values will be maintained. Software driver code
must wait 3 s following a software reset before allowing
further serial MII operations with the DP83849C.
6.3 Soft Reset
A partial software reset can be initiated by setting the Soft
Reset bit (bit 9) in the PHYCR2 Register. Setting this bit will
reset all transmit and receive operations, but will not reset
the register space. All register configurations will be pre-
served. Register space will remain available following a
Soft Reset.