DP83849CVS/NOPB National Semiconductor, DP83849CVS/NOPB Datasheet - Page 79

• Manufacturer Part Number: DP83849CVS/NOPB
• Description: IC TXRX ETHERNET PHY DUAL 80TQFP
• Manufacturer: National Semiconductor
• Type: Transceiverr

Specifications of DP83849CVS/NOPB

• Number Of Drivers/receivers: 2/2
• Protocol: Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP, 80-VQFP
• Data Rate: 100Mbps
• Supply Voltage Range: 3V To 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 80
• Operating Temperature Range: 0°C To +70°C
• Msl: MSL 3 - 168 Hours
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Data Rate Max: 10Mbps
• For Use With: DP83849CVS-EVK - BOARD EVALUATION DP83849CVS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DP83849CVS; *DP83849CVS/NOPB; DP83849CVS

8.2.2 Reset Timing
Note: It is important to choose pull-up and/or pull-down resistors for each of the hardware configuration pins that provide
fast RC time constants in order to latch-in the proper value prior to the pin transitioning to an output driver.
T2.2.1
T2.2.2
T2.2.3
T2.2.4
Dual Function Pins
Become Enabled As Outputs
Parameter
Latch-In of Hardware
Configuration Pins
RESET_N
Hardware
X1 clock
Post RESET Stabilization time
prior to MDC preamble for reg-
ister accesses
Hardware Configuration Latch-
in Time from the Deassertion
of RESET (either soft or hard)
Hardware Configuration pins
transition to output drivers
RESET pulse width
MDC
Vcc
Description
MDIO is pulled high for 32-bit serial man-
agement initialization
Hardware Configuration Pins are de-
scribed in the Pin Description section
X1 Clock must be stable for at min. of 1us
during RESET pulse low time.
T2.2.4
79
T2.2.2
T2.2.1
Notes
input
T2.2.3
output
Min
1
32 clocks
Typ
50
3
3
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Max
Units
ns
s
s
s