DP83849CVS/NOPB National Semiconductor, DP83849CVS/NOPB Datasheet - Page 81

• Manufacturer Part Number: DP83849CVS/NOPB
• Description: IC TXRX ETHERNET PHY DUAL 80TQFP
• Manufacturer: National Semiconductor
• Type: Transceiverr

Specifications of DP83849CVS/NOPB

• Number Of Drivers/receivers: 2/2
• Protocol: Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP, 80-VQFP
• Data Rate: 100Mbps
• Supply Voltage Range: 3V To 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 80
• Operating Temperature Range: 0°C To +70°C
• Msl: MSL 3 - 168 Hours
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Data Rate Max: 10Mbps
• For Use With: DP83849CVS-EVK - BOARD EVALUATION DP83849CVS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DP83849CVS; *DP83849CVS/NOPB; DP83849CVS

8.2.5 100 Mb/s MII Receive Timing
Note: RX_CLK may be held low or high for a longer period of time during transition between reference and recovered
clocks. Minimum high and low times will not be violated.
8.2.6 100BASE-TX MII Transmit Packet Latency Timing
Note: For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after
the assertion of TX_EN to the first bit of the “J” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100
Mb/s mode.
T2.5.1
T2.5.2
Parameter
T2.6.1
Parameter
PMD Output Pair
RX_CLK
RXD[3:0]
RX_DV
RX_ER
RX_CLK High/Low Time
RX_CLK to RXD[3:0], RX_DV, RX_ER Delay 100 Mb/s Normal mode
TX_CLK to PMD Output Pair
Latency
TX_CLK
TX_EN
TXD
Description
T2.5.2
Description
T2.5.1
IDLE
100BASE-TX mode
T2.6.1
81
Valid Data
100 Mb/s Normal mode
Notes
(J/K)
Notes
T2.5.1
DATA
Min
Min
16
10
Typ
5
Typ
20
Max
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Max
24
30
Units
bits
Units
ns
ns