DP83849CVS/NOPB National Semiconductor, DP83849CVS/NOPB Datasheet - Page 78

• Manufacturer Part Number: DP83849CVS/NOPB
• Description: IC TXRX ETHERNET PHY DUAL 80TQFP
• Manufacturer: National Semiconductor
• Type: Transceiverr

Specifications of DP83849CVS/NOPB

• Number Of Drivers/receivers: 2/2
• Protocol: Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP, 80-VQFP
• Data Rate: 100Mbps
• Supply Voltage Range: 3V To 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 80
• Operating Temperature Range: 0°C To +70°C
• Msl: MSL 3 - 168 Hours
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Data Rate Max: 10Mbps
• For Use With: DP83849CVS-EVK - BOARD EVALUATION DP83849CVS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DP83849CVS; *DP83849CVS/NOPB; DP83849CVS

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8.2 AC Specs
8.2.1 Power Up Timing
Note: In RMII Mode, the minimum Post Power up Stabilization and Hardware Configuration Latch-in times are 84ms.
T2.1.1
T2.1.2
T2.1.3
Dual Function Pins
Become Enabled As Outputs
Parameter
Latch-In of Hardware
Configuration Pins
RESET_N
Hardware
X1 clock
Post Power Up Stabilization
time prior to MDC preamble for
register accesses
Hardware Configuration Latch-
in Time from power up
Hardware Configuration pins
transition to output drivers
MDC
Vcc
Description
MDIO is pulled high for 32-bit serial man-
agement initialization
X1 Clock must be stable for a min. of
167ms at power up.
Hardware Configuration Pins are de-
scribed in the Pin Description section
X1 Clock must be stable for a min. of
167ms at power up.
T2.1.2
T2.1.1
78
Notes
input
T2.1.3
output
Min
167
167
32 clocks
Typ
50
Max
Units
ms
ms
ns