DP83849CVS/NOPB National Semiconductor, DP83849CVS/NOPB Datasheet - Page 59

• Manufacturer Part Number: DP83849CVS/NOPB
• Description: IC TXRX ETHERNET PHY DUAL 80TQFP
• Manufacturer: National Semiconductor
• Type: Transceiverr

Specifications of DP83849CVS/NOPB

• Number Of Drivers/receivers: 2/2
• Protocol: Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP, 80-VQFP
• Data Rate: 100Mbps
• Supply Voltage Range: 3V To 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 80
• Operating Temperature Range: 0°C To +70°C
• Msl: MSL 3 - 168 Hours
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Data Rate Max: 10Mbps
• For Use With: DP83849CVS-EVK - BOARD EVALUATION DP83849CVS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DP83849CVS; *DP83849CVS/NOPB; DP83849CVS

7.1.11 MII Interrupt Control Register (MICR)
This register implements the MII Interrupt PHY Specific Control register. Sources for interrupt generation include: Energy
Detect State Change, Link State Change, Speed Status Change, Duplex Status Change, Auto-Negotiation Complete or
any of the counters becoming half-full. The individual interrupt events must be enabled by setting bits in the MII Interrupt
Status and Event Control Register (MISR).
7.1.12 MII Interrupt Status and Misc. Control Register (MISR)
This register contains event status and enables for the interrupt function. If an event has occurred since the last read of
this register, the corresponding status bit will be set. If the corresponding enable bit in the register is set, an interrupt will
be generated if the event occurs. The MICR register controls must also be set to allow interrupts. The status indications
in this register will be set even if the interrupt is not enabled.
15:3
Bit
15
14
13
12
2
1
0
RESERVED
LINK_INT
Bit Name
SPD_INT
Table 31. MII Interrupt Status and Misc. Control Register (MISR), address 12h
INT_OE
LQ_INT
ED_INT
INTEN
TINT
Table 30. MII Interrupt Control Register (MICR), address 11h
0, RO/COR
0, RO/COR
0, RO/COR
0, RO/COR
Default
0, RW
0, RW
0, RW
0, RO
RESERVED: Writes ignored, read as 0.
Test Interrupt:
Forces the PHY to generate an interrupt to facilitate interrupt test-
ing. Interrupts will continue to be generated as long as this bit re-
mains set.
1 = Generate an interrupt
0 = Do not generate interrupt
Interrupt Enable:
Enable interrupt dependent on the event enables in the MISR reg-
ister.
1 = Enable event based interrupts
0 = Disable event based interrupts
Interrupt Output Enable:
Enable interrupt events to signal via the PWRDOWN_INT pin by
configuring the PWRDOWN_INT pin as an output.
1 = PWRDOWN_INT is an Interrupt Output
0 = PWRDOWN_INT is a Power Down Input
Link Quality interrupt:
1 = Link Quality interrupt is pending and is cleared by the current
read.
0 = No Link Quality interrupt pending.
Energy Detect interrupt:
1 = Energy detect interrupt is pending and is cleared by the current
read.
0 = No energy detect interrupt pending.
Change of Link Status interrupt:
1 = Change of link status interrupt is pending and is cleared by the
current read.
0 = No change of link status interrupt pending.
Change of speed status interrupt:
1 = Speed status change interrupt is pending and is cleared by the
current read.
0 = No speed status change interrupt pending.
59
Description
www.national.com