DP83849CVS/NOPB National Semiconductor, DP83849CVS/NOPB Datasheet - Page 75

• Manufacturer Part Number: DP83849CVS/NOPB
• Description: IC TXRX ETHERNET PHY DUAL 80TQFP
• Manufacturer: National Semiconductor
• Type: Transceiverr

Specifications of DP83849CVS/NOPB

• Number Of Drivers/receivers: 2/2
• Protocol: Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP, 80-VQFP
• Data Rate: 100Mbps
• Supply Voltage Range: 3V To 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 80
• Operating Temperature Range: 0°C To +70°C
• Msl: MSL 3 - 168 Hours
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Data Rate Max: 10Mbps
• For Use With: DP83849CVS-EVK - BOARD EVALUATION DP83849CVS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DP83849CVS; *DP83849CVS/NOPB; DP83849CVS

7.3.10 Link Quality Data Register (LQDR), Page 2
This register provides read/write control of thresholds for the 100Mb Link Quality Monitor function. The register also pro-
vides a mechanism for reading current adapted parameter values. Threshold values may not be written if the device is
powered-down
15:14
11:9
Bit
7:0
13
12
8
SAMPLE_PARAM
LQ_PARAM_SEL
WRITE_LQ_THR
.
LQ_THR_DATA
LQ_THR_SEL
RESERVED
Bit Name
Table 52. Link Quality Data Register (LQDR), address 1Eh
Default
0, RW
0, RW
0, RW
0, RW
0, RW
0, RO
RESERVED: Writes ignored, read as 0.
Sample DSP Parameter:
Setting this bit to a 1 enables reading of current parameter values
and initiates sampling of the parameter value. The parameter to be
read is selected by the LQ_PARAM_SEL bits.
Write Link Quality Threshold:
Setting this bit will cause a write to the Threshold register selected
by LQ_PARAM_SEL and LQ_THR_SEL. The data written is con-
tained in LQ_THR_DATA. This bit will always read back as 0.
Link Quality Parameter Select:
This 3-bit field selects the Link Quality Parameter. This field is used
for sampling current parameter values as well as for reads/writes to
Threshold values. The following encodings are available:
000: DEQ_C1
001: DAGC
010: DBLW
011: Frequency Offset
100: Frequency Control
Link Quality Threshold Select:
This bit selects the Link Quality Threshold to be read or written. A
0 selects the Low threshold, while a 1 selects the high threshold.
When combined with the LQ_PARAM_SEL field, the following en-
codings are available {LQ_PARAM_SEL, LQ_THR_SEL}:
000,0: DEQ_C1 Low
000,1: DEQ_C1 High
001,0: DAGC Low
001,1: DAGC High
010,0: DBLW Low
010,1: DBLW High
011,0: Frequency Offset Low
011,1: Frequency Offset High
100,0: Frequency Control Low
100,1: Frequency Control High
Link Quality Threshold Data:
The operation of this field is dependent on the value of the
Sample_Param bit.
If Sample_Param = 0:
On a write, this value contains the data to be written to the selected
Link Quality Threshold register.
On a read, this value contains the current data in the selected Link
Quality Threshold register.
If Sample_Param = 1:
On a read, this value contains the sampled parameter value. This
value will remain unchanged until a new read sequence is started.
75
Description
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