ADV7181BCP Analog Devices Inc, ADV7181BCP Datasheet - Page 29

• Manufacturer Part Number: ADV7181BCP
• Description: IC VIDEO DECODER NTSC 64-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7181BCP

• Applications: Recorders, Set-Top Boxes
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Adc/dac Resolution: 9b
• Screening Level: Industrial
• Package Type: LFCSP EP
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: EVAL-ADV7181BEB - BOARD EVALUATION FOR ADV7181
• Lead Free Status / RoHS Status: Compliant, Contains lead / RoHS non-compliant

CSFM[2:0] C Shaping Filter Mode, Address 0x17[7]
The C shaping filter mode bits allow the user to select from a
range of low-pass filters, SH1 to SH5 and wideband mode, for
the chrominance signal. The autoselection options automati-
cally select from the filter options to give the specified response;
see settings 000 and 001 in Table 31.
Table 31. CSFM Function
CSFM[2:0]
000 (default)
001
010
011
100
101
110
111
Figure 15 shows the responses of SH1 (narrowest) to SH5
(widest) in addition to the wideband mode (in red).
–10
–20
–30
–40
–50
–60
0
0
Figure 15. Chroma Shaping Filter Responses
1
Description
Autoselect 1.5 MHz bandwidth
Autoselect 2.17 MHz bandwidth
SH1
SH2
SH3
SH4
SH5
Wideband mode
COMBINED C ANTIALIAS, C SHAPING FILTER,
2
MINIMUM
VOLTAGE
FREQUENCY (MHz)
C RESAMPLER
MAXIMUM
VOLTAGE
3
4
CLAMP
LEVEL
5
6
Figure 16. Gain Control Overview
Rev. B | Page 29 of 100
ANALOG VOLTAGE
RANGE SUPPORTED BY ADC (1.6V RANGE FOR ADV7181B)
ADC
GAIN OPERATION
The gain control within the ADV7181B is done on a purely
digital basis. The input ADCs support a 9-bit range, mapped
into a 1.6 V analog voltage range. Gain correction takes place
after the digitization in the form of a digital multiplier.
Advantages of this architecture over the commonly used
programmable gain amplifier (PGA) before the ADC include
the fact that the gain is now completely independent of supply,
temperature, and process variations.
As shown in Figure 16, the ADV7181B can decode a video
signal as long as it fits into the ADC window. The components
to this are the amplitude of the input signal and the dc level it
resides on. The dc level is set by the clamping circuitry (see the
Clamp Operation section).
If the amplitude of the analog video signal is too high, clipping
can occur, resulting in visual artifacts. The analog input range
of the ADC, together with the clamp level, determines the
maximum supported amplitude of the video signal.
The minimum supported amplitude of the input video is
determined by the ADV7181B’s ability to retrieve horizontal
and vertical timing and to lock to the color burst, if present.
There are separate gain control units for luma and chroma data.
Both can operate independently of each other. The chroma unit,
however, can also take its gain value from the luma path.
The possible AGC modes are summarized in Table 32.
It is possible to freeze the automatic gain control loops. This
causes the loops to stop updating. It also causes the AGC
determined gain at the time of the freeze to stay active until the
loop is either unfrozen or the gain mode of operation is
changed.
The currently active gain from any of the modes can be read
back. Refer to the description of the dual-function manual gain
registers, LG[11:0] Luma Gain and CG[11:0] Chroma Gain, in
the Luma Gain and the Chroma Gain sections.
PROCESSOR
DATA PRE-
(DPP)
SDP
(GAIN SELECTION ONLY)
CONTROL
GAIN
ADV7181B