ADV7181BCP Analog Devices Inc, ADV7181BCP Datasheet - Page 45

• Manufacturer Part Number: ADV7181BCP
• Description: IC VIDEO DECODER NTSC 64-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7181BCP

• Applications: Recorders, Set-Top Boxes
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Adc/dac Resolution: 9b
• Screening Level: Industrial
• Package Type: LFCSP EP
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: EVAL-ADV7181BEB - BOARD EVALUATION FOR ADV7181
• Lead Free Status / RoHS Status: Compliant, Contains lead / RoHS non-compliant

PVBEGDELO PAL Vsync Begin Delay on Odd Field,
Address 0xE8[7]
When PVBEGDELO is 0 (default), there is no delay.
Setting PVBEGDELO to 1 delays Vsync going high on an odd
field by a line relative to PVBEG.
PVBEGDELE PAL Vsync Begin Delay on Even Field,
Address 0xE8[6]
When PVBEGDELE is 0, there is no delay.
Setting PVBEGDELE to 1 (default) delays Vsync going high on
an even field by a line relative to PVBEG.
PVBEGSIGN PAL Vsync Begin Sign, Address 0xE8[5]
Setting PVBEGSIGN to 0 delays the beginning of Vsync. Set for
user manual programming.
Setting PVBEGSIGN to 1(default) advances the beginning of
Vsync. Not recommended for user programming.
PVBEG[4:0] PAL Vsync Begin, Address 0xE8[4:0]
The default value of PVBEG is 00101, indicating the PAL Vsync
begin position.
NOT VALID FOR USER
PROGRAMMING
VSYNC BY PVBEG[4:0]
ADVANCE BEGIN OF
ADVANCE BY
PVBEGDELO
ADDITIONAL
DELAY BY
0.5 LINE
VSBHO
1 LINE
YES
1
1
Figure 27. PAL Vsync Begin
1
VSYNC BEGIN
0
0
ODD FIELD?
PVBEGSIGN
0
0
VSYNC BY PVBEG[4:0]
DELAY BEGIN OF
ADVANCE BY
PVBEGDELE
ADDITIONAL
DELAY BY
0
0.5 LINE
VSBHE
1 LINE
NO
1
1
Rev. B | Page 45 of 100
For all NTSC/PAL Vsync timing controls, both the V bit in the
AV code and the Vsync on the VS pin are modified.
PVENDDELO PAL Vsync End Delay on Odd Field,
Address 0xE9[7]
When PVENDDELO is 0 (default), there is no delay.
Setting PVENDDELO to 1 delays Vsync going low on an odd
field by a line relative to PVEND.
PVENDDELE PAL Vsync End Delay on Even Field,
Address 0xE9[6]
When PVENDDELE is 0 (default), there is no delay.
Setting PVENDDELE to 1 delays Vsync going low on an even
field by a line relative to PVEND.
PVENDSIGN PAL Vsync End Sign, Address 0xE9[5]
Setting PVENDSIGN to 0 (default) delays the end of Vsync.
Set for user manual programming.
Setting PVENDSIGN to 1 advances the end of Vsync. Not
recommended for user programming.
NOT VALID FOR USER
PROGRAMMING
VSYNC BY PVEND[4:0]
ADVANCE END OF
ADVANCE BY
PVENDDELO
ADDITIONAL
DELAY BY
0.5 LINE
VSEHO
1 LINE
YES
1
1
Figure 28. PAL Vsync End
1
0
0
ODD FIELD?
PVENDSIGN
VSYNC END
0
0
DELAY END OF VSYNC
BY PVEND[4:0]
ADVANCE BY
ADDITIONAL
PVENDDELE
DELAY BY
0
0.5 LINE
VSEHE
1 LINE
ADV7181B
NO
1
1