ADV7181BCP Analog Devices Inc, ADV7181BCP Datasheet - Page 39

• Manufacturer Part Number: ADV7181BCP
• Description: IC VIDEO DECODER NTSC 64-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7181BCP

• Applications: Recorders, Set-Top Boxes
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Adc/dac Resolution: 9b
• Screening Level: Industrial
• Package Type: LFCSP EP
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: EVAL-ADV7181BEB - BOARD EVALUATION FOR ADV7181
• Lead Free Status / RoHS Status: Compliant, Contains lead / RoHS non-compliant

VS and FIELD Configuration
The following controls allow the user to configure the behavior
of the VS and FIELD output pins, as well as the generation of
embedded AV codes:
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NEWAVMODE New AV Mode, Address 0x31[4]
When NEWAVMODE is 0, EAV/SAV codes are generated to
suit ADI encoders. No adjustments are possible.
Setting NEWAVMODE to 1 (default) enables the manual posit-
ion of the VSYNC, Field, and AV codes using Register 0x34 to
Register 0x37 and Register 0xE5 to Register 0xEA. Default
register settings are CCIR656 compliant; see Figure 20 for
NTSC and Figure 25 for PAL. For recommended manual user
settings, see Table 55 for NTSC and see Table 56 and Figure 26
for PAL.
HVSTIM Horizontal VS Timing, Address 0x31[3]
The HVSTIM bit allows the user to select where the VS signal is
asserted within a line of video. Some interface circuitry can
require VS to go low while HS is low.
When HVSTIM is 0 (default), the start of the line is relative
to HSE.
When HVSTIM is 1, the start of the line is relative to HSB.
ADV encoder-compatible signals via NEWAVMODE
PVS, PF
HVSTIM
VSBHO, VSBHE
VSEHO, VSEHE
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For PAL control
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For NTSC control
NVBEGDELO, NVBEGDELE, NVBEGSIGN,
NVBEG[4:0]
NVENDDELO, NVENDDELE, NVENDSIGN,
NVEND[4:0]
NFTOGDELO, NFTOGDELE, NFTOGSIGN,
NFTOG[4:0]
PVBEGDELO, PVBEGDELE, PVBEGSIGN,
PVBEG[4:0]
PVENDDELO, PVENDDELE, PVENDSIGN,
PVEND[4:0]
PFTOGDELO, PFTOGDELE, PFTOGSIGN,
PFTOG[4:0]
Rev. B | Page 39 of 100
VSBHO VS Begin Horizontal Position Odd,
Address 0x32[7]
The VSBHO and VSBHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to only change state
when HS is high/low.
When VSBHO is 0 (default), the VS pin goes high at the middle
of a line of video (odd field).
When VSBHO is 1, the VS pin changes state at the start of a line
(odd field).
VSBHE VS Begin Horizontal Position Even,
Address 0x32[6]
The VSBHO and VSBHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to only change state
when HS is high/low.
When VSBHE is 0 (default), the VS pin goes high at the middle
of a line of video (even field).
When VSBHE is 1, the VS pin changes state at the start of a line
(even field).
VSEHO VS End Horizontal Position Odd,
Address 0x33[7]
The VSEHO and VSEHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to only change state
when HS is high/low.
When VSEHO is 0 (default), the VS pin goes low (inactive) at
the middle of a line of video (odd field).
When VSEHO is 1, the VS pin changes state at the start of a line
(odd field).
VSEHE VS End Horizontal Position Even,
Address 0x33[6]
The VSEHO and VSEHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to only change state
when HS is high/low.
When VSEHE is 0, the VS pin goes low (inactive) at the middle
of a line of video (even field).
When VSEHE is 1 (default), the VS pin changes state at the start
of a line (even field).
PVS Polarity VS, Address 0x37[5]
The polarity of the VS pin can be inverted using the PVS bit.
When PVS is 0 (default), VS is active high.
When PVS is 1, VS is active low.
ADV7181B