ADV7181BCP Analog Devices Inc, ADV7181BCP Datasheet - Page 57

• Manufacturer Part Number: ADV7181BCP
• Description: IC VIDEO DECODER NTSC 64-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7181BCP

• Applications: Recorders, Set-Top Boxes
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Adc/dac Resolution: 9b
• Screening Level: Industrial
• Package Type: LFCSP EP
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: EVAL-ADV7181BEB - BOARD EVALUATION FOR ADV7181
• Lead Free Status / RoHS Status: Compliant, Contains lead / RoHS non-compliant

IF Compensation Filter
IF FILTSEL[2:0] IF Filter Select Address 0xF8[2:0]
The IF FILTSEL[2:0] register allows the user to compensate
for SAW filter characteristics on a composite input as would
be observed on tuner outputs. Figure 35 and Figure 36 show
IF filter compensation for NTSC and PAL.
The options for this feature are as follows:
•
•
•
See Table 85 for programming details.
Bypass mode (default)
NTSC—consists of three filter characteristics
PAL—consists of three filter characteristics
–10
–12
–2
–4
–6
–8
–2
–4
–6
–8
6
4
2
0
6
4
2
0
2.0
3.0
Figure 35. NTSC IF Compensation Filter Responses
Figure 36. PAL IF Compensation Filter Responses
2.5
3.5
3.0
4.0
FREQUENCY (MHz)
FREQUENCY (MHz)
3.5
4.5
4.0
5.0
4.5
5.5
5.0
6.0
Rev. B | Page 57 of 100
I
The ADV7181B has a comprehensive interrupt register set. This
map is located in Register Access Page 2. See Table 83 or details
of the interrupt register map.
Steps to access this map are presented in Figure 37.
Interrupt Request Output Operation
When an interrupt event occurs, the interrupt pin INTRQ
goes low with a programmable duration given by
INTRQ_DUR_SEL[1:0]
INTRQ_DURSEL[1:0], Interrupt Duration Select
Address 0x40 (Interrupt Space)[7:6]
Table 75. INTRQ_DUR_SEL
INTRQ_DURSEL[1:0]
00
01
10
11
When the active until cleared interrupt duration is selected and
the event that caused the interrupt is no longer in force, the
interrupt persists until it is masked or cleared.
For example, if the ADV7181B loses lock, an interrupt is
generated and the INTRQ pin goes low. If the ADV7181B
returns to the locked state, INTRQ continues to drive low
until the SD_LOCK bit is either masked or cleared.
Interrupt Drive Level
The ADV7181B resets with open drain enabled and all interrupts
masked off. Therefore, INTRQ is in a high impedance state after
reset. 01 or 10 must to be written to INTRQ_OP_SEL[1:0] for a
logic level to be driven out from the INTRQ pin.
It is also possible to write to a register in the ADV7181B that
manually asserts the INTRQ pin. This bit is MPU_STIM_INTRQ.
2
C Interrupt System
ADDRESS 0x0E BIT 6, 5 = 00b
REGISTER ACCESS PAGE 1
NORMAL REGISTER SPACE
ADDRESS 0x40 ≥ 0xFF
ADDRESS 0x00 ≥ 0x3F
COMMON I
I
2
C SPACE
Figure 37. Register Access, Page 1 and Page 2
2
C SPACE
Description
3 Xtal periods (default)
15 Xtal periods
63 Xtal periods
Active until cleared
INTERRUPT REGISTER SPACE
ADDRESS 0x0E BIT 6, 5 = 01b
REGISTER ACCESS PAGE 2
ADDRESS 0x40 ≥ 0x4C
I
2
C SPACE
ADV7181B