ADV7181BCP Analog Devices Inc, ADV7181BCP Datasheet - Page 8

• Manufacturer Part Number: ADV7181BCP
• Description: IC VIDEO DECODER NTSC 64-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7181BCP

• Applications: Recorders, Set-Top Boxes
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Adc/dac Resolution: 9b
• Screening Level: Industrial
• Package Type: LFCSP EP
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: EVAL-ADV7181BEB - BOARD EVALUATION FOR ADV7181
• Lead Free Status / RoHS Status: Compliant, Contains lead / RoHS non-compliant

ADV7181B
TIMING SPECIFICATIONS
Guaranteed by characterization. A
operating temperature range, unless otherwise noted.
Table 3.
Parameter
SYSTEM CLOCK AND CRYSTAL
I
RESET FEATURE
CLOCK OUTPUTS
DATA AND CONTROL OUTPUTS
1
2
ANALOG SPECIFICATIONS
Guaranteed by characterization. A
operating temperature range, unless otherwise noted. Recommended analog input video signal range: 0.5 V to 1.6 V, typically 1 V p-p.
Table 4.
Parameter
CLAMP CIRCUITRY
1
2
2
Temperature range: T
The min/max specifications are guaranteed over this range.
Temperature range: T
The min/max specifications are guaranteed over this range.
C PORT
Nominal Frequency
Frequency Stability
SCLK Frequency
SCLK Min Pulse Width High
SCLK Min Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDA Setup Time
SCLK and SDA Rise Time
SCLK and SDA Fall Time
Setup Time for Stop Condition
Reset Pulse Width
LLC1 Mark Space Ratio
Data Output Transitional Time
Data Output Transitional Time
External Clamp Capacitor
Input Impedance
Large Clamp Source Current
Large Clamp Sink Current
Fine Clamp Source Current
Fine Clamp Sink Current
1, 2
1, 2
MIN
MIN
to T
to T
MAX
MAX
, –40°C to +85°C.
, –40°C to +85°C
VDD
VDD
= 3.15 V to 3.45 V, D
= 3.15 V to 3.45 V, D
Symbol
Symbol
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
11
12
:t
10
Test Conditions
Clamps switched off
VDD
VDD
Rev. B | Page 8 of 100
Test Conditions
Negative clock edge to start of
valid data (t
End of valid data to negative
clock edge (t
= 1.65 V to 2.0 V, D
= 1.65 V to 2.0 V, D
ACCESS
HOLD
= t
= t
10
9
VDDIO
VDDIO
+ t
– t
12
11
)
= 3.0 V to 3.6 V, P
= 3.0 V to 3.6 V, P
)
Min
0.6
1.3
0.6
0.6
100
5
45:55
VDD
Typ
0.6
VDD
27.00
Min
= 1.65 V to 2.0 V;
= 1.65 V to 2.0 V;
Max
±50
400
300
300
55:45
3.4
2.4
Typ
0.1
10
0.75
0.75
60
60
Unit
MHz
ppm
kHz
μs
μs
μs
μs
ns
ns
ns
μs
ms
% duty cycle
ns
ns
Max
Unit
μF
MΩ
mA
mA
μA
μA