X96012V14I Intersil, X96012V14I Datasheet - Page 14

• Manufacturer Part Number: X96012V14I
• Description: IC CNTRLR UNIV MEM/DAC 14-TSSOP
• Manufacturer: Intersil
• Type: Controllerr

Specifications of X96012V14I

• Input Type: *
• Output Type: *
• Interface: 2-Wire Serial
• Current - Supply: *
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Look-Up Tables
The X96012 memory array contains two 64-byte look-up
tables. One is associated to pin I1’s output current generator
and the other to pin I2’s output current generator, through
their corresponding D/A converters. The output of each
look-up table is the byte contained in the selected row. By
default these bytes are the inputs to the D/A converters
driving pins I1 and I2.
The byte address of the selected row is obtained by adding
the look-up table base address (90h for LUT1, and D0h for
LUT2) and the appropriate row selection bits. See Figure 9.
By default, the look-up table selection bits are the 6
MSBs of the A/D converter output. Alternatively, the A/D
converter can be bypassed and the six row selection bits
are the six LSBs of Control Registers 1 and 2, for the
LUT1 and LUT2 respectively. The selection between
these options is illustrated in Figure 10, and described in
“I2DS: Current Generator 2 Direction Select Bit (Non-volatile)”
on page 9, and “Control Register 2” on page 10.
INPUT BYTE
DAC1 OR
DAC2
VREF
14
VOLTAGE
3 AND 2 IN CONTROL
DIVIDER
BITS 1 AND 0, OR
OR I2FSO[1:0]
REGISTER 5
6 OR 7 IN CONTROL
I1DS OR I2DS: BITS
I1FSO[1:0]
FIGURE 8. D/A CONVERTER BLOCK DIAGRAM
REGISTER 0.
+
-
VSS
X96012
11
POLARITY
CIRCUIT
SELECT
VSS
VCC
10
Current Generator Block
The Current Generator pins I1 and I2 are outputs of two
independent current mode D/A converters.
D/A Converter Operation
The Block Diagram for each of the D/A converters is shown
in Figure 8.
The input byte of the D/A converter selects a voltage on the
non-inverting input of an operational amplifier. The output of
the amplifier drives the gate of a FET, whose source is
connected to ground via resistor R
fed back to the inverting input of the amplifier. The drain of
the FET is connected to the output current pin (I1 or I2) via a
“polarity select” circuit block.
01
00
VSS
R1 OR R2 PIN
VSS
R1_EXTERNAL OR R2_EXTERNAL
OPTIONAL EXTERNAL RESISTOR
I1 OR I2 PIN
1
or R
2
. This node is also
February 20, 2008
FN8216.3