X96012V14I Intersil, X96012V14I Datasheet - Page 4

• Manufacturer Part Number: X96012V14I
• Description: IC CNTRLR UNIV MEM/DAC 14-TSSOP
• Manufacturer: Intersil
• Type: Controllerr

Specifications of X96012V14I

• Input Type: *
• Output Type: *
• Interface: 2-Wire Serial
• Current - Supply: *
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Electrical Specifications
NOTES:
D/A Converter Characteristics
I
V
V
V
IFS
IFS
IFS
IFS
Offset
FSError
DNL
INL
V
V
2. These parameters are periodically sampled and not 100% tested.
3. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.
4. The device goes into Standby: 200ns after any STOP, except those that initiate a nonvolatile write cycle. It goes into Standby t
5. t
6. For this range of V(V
7. These parameters are periodically sampled and not 100% tested.
8. TCO
R
ADCOK
POR
CC
SYMBOL
ISink
ISource
that initiates a nonvolatile write cycle. It also goes into Standby 9 clock cycles after any START that is not followed by the correct Slave Address
Byte.
minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
00
01
10
11
DAC
Ramp
WC
DAC
SYMBOL
DAC
is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the
ref
DAC
= [Max V(V
I1 or I2 Full Scale Current, with External Resistor
Setting
I1 or I2 Full Scale Current, with Internal Low
Current Setting Option
I1 or I2 Full Scale Current, with Internal Middle
Current Setting Option
I1 or I2 Full Scale Current, with Internal High
Current Setting Option
I1 or I2 D/A Converter Offset Error
I1 or I2 D/A Converter Full Scale Error
I1 or I2 D/A Converter Differential Nonlinearity
I1 or I2 D/A Converter Integral Nonlinearity with
Respect to a Straight Line Through 0 and the Full
Scale Value
I1 or I2 Sink Voltage Compliance
I1 or I2 Source Voltage Compliance
Current from pin R1 or R2 to VSS
Power-on Reset Threshold
Voltage
V
ADC Enable Minimum Voltage
REF
CC
REF
) - Min V(V
Ramp Rate
) the full scale sink mode current at I1 and I2 follows V(V
PARAMETER
PARAMETER
4
Conditions are as follows, unless otherwise specified. All typical values are for T
Maximum and minimum specifications are over the recommended operating conditions. All voltages are
referred to the voltage at pin V
R
external 2kΩ resistor. 2-wire interface in “standby” (see Notes 9 and 10 on page 5). WP, A0, A1, and A2 floating.
V
REF
1
REF
and V
)] x 10
pin unloaded. (Continued)
(See “Electrical Specifications” table starting on page 3 for standard conditions).
SS
, and another between R
6
/(1.21V x +140°C).
Figure 11
(Notes 9, 12)
(Notes 2, 9, 13)
DAC input Byte = FFh,
Source or sink mode, V(I1) and V(I2)
are V
1.2V in sink mode.
(Notes 10, 11)
(Note 12)
(Notes 2, 13)
(Note 12)
(Notes 2, 13)
SS
X96012
TEST CONDITIONS
. All bits in control registers are “0”. 255Ω, 0.1%, resistor connected between
CC
2
and V
TEST CONDITIONS
- 1.2V in source mode and
SS
. 400kHz TTL input at SCL. SDA pulled to V
REF
) with a linearity error smaller than 1%.
(Note 3)
MIN
2.6
1.5
0.2
(Note 3)
0
MIN
1.56
0.64
-0.5
0.3
1.2
2.5
-2
-1
1
1
0
0
A
TYP
= +25°C and 5V at pin V
TYP
1.58
0.85
0.4
1.3
CC
(Note 3)
V
V
(Note 3)
MAX
3200
CC
CC
2.8
2.8
MAX
through an
50
1.06
V
V
WC
1.6
3.2
0.5
1.6
0.5
1
2
1
CC
CC
- 1.2
- 2.5
February 20, 2008
after a STOP
mV/µs
FN8216.3
UNIT
UNIT
LSB
LSB
LSB
LSB
mA
mA
mA
mA
mA
µA
V
V
V
V
V
V
CC
.