FIN3385MTDX Fairchild Semiconductor, FIN3385MTDX Datasheet - Page 9

• Manufacturer Part Number: FIN3385MTDX
• Description: IC SERIALIZER/DESERIAL 56-TSSOP
• Manufacturer: Fairchild Semiconductor
• Type: Low Voltage 28-Bit Flat Panel Display Linkr

Specifications of FIN3385MTDX

• Function: Serializer/Deserializer
• Data Rate: 2.38Gbps
• Input Type: LVTTL
• Output Type: LVDS
• Number Of Inputs: 28
• Number Of Outputs: 4
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Ic Output Type: LVDS
• No. Of Inputs: 28
• No. Of Outputs: 4
• Supply Voltage Range: 3V To 3.6V
• Driver Case Style: TSSOP
• No. Of Pins: 56
• Termination Type: SMD
• Rohs Compliant: Yes
• Number Of Drivers: 4
• Number Of Receivers: 28
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 150 C
• Minimum Operating Temperature: - 65 C
• Mounting Style: SMD/SMT
• Supply Current: 41.8 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Filter Terminals: SMD
• Digital Ic Case Style: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: FIN3385MTDX; FIN3385MTDXTR

© 2003 Fairchild Semiconductor Corporation
FIN3383/3384/3385/3386 • Rev. 1.0.4
Transmitter AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified.
Transmitter Output Data Jitter (f=85MHz)
Notes:
12. Outputs of all transmitters stay in 3-STATE until power reaches 2V. Clock and data output begins to toggle
13. This output data pulse position works for both transmitters for TTL inputs, except the LVDS output bit mapping
14. This jitter specification is based on the assumption that PLL has a reference clock with cycle-to-cycle input
t
t
t
t
t
t
t
t
TPPB0
TPPB1
TPPB2
TPPB3
TPPB4
TPPB5
TPPB6
TPLLS
t
10ms after V
difference (see Figure 18). Figure 20 shows the skew between the first data bit and clock output. A two-bit
cycle delay is guaranteed when the MSB is output from transmitter.
jitter of less than 2ns.
JCC
Transmitter Output Pulse Position of Bit 0
Transmitter Output Pulse Position of Bit 1
Transmitter Output Pulse Position of Bit 2
Transmitter Output Pulse Position of Bit 3
Transmitter Output Pulse Position of Bit 4
Transmitter Output Pulse Position of Bit 5
Transmitter Output Pulse Position of Bit 6
FIN3385
Transmitter Clock Out Jitter, Cycle-to-Cycle
Figure 20
Transmitter Phase Lock Loop Set Time
CC
reaches 3V and /PwrDn pin is above 1.5V.
(13)
(14)
9
Figure 20
f=40MHz
f=65MHz
f=85MHz
Figure 26
a
=
f
×
1
7
(13)
2a-0.2
3a-0.2
4a-0.2
5a-0.2
6a-0.2
a-0.2
-0.2
350
210
110
2a
3a
4a
5a
6a
0
a
2a+0.2
3a+0.2
4a+0.2
5a+0.2
6a+0.2
a+0.2
370
230
150
0.2
10
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ms
ns
ns
ns
ns
ns
ns
ns
ps