FSAL200QSCX Fairchild Semiconductor, FSAL200QSCX Datasheet
FSAL200QSCX
Specifications of FSAL200QSCX
FSAL200QSCXTR
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FSAL200QSCX Summary of contents
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... Thin Shrink Small Outline Package(TSSOP), JEDEC MO-153, 4.4mm Wide FSAL200QSC 16-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide FSAL200QSCX 16-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide All packages are Pb-free per JEDEC standard J-SDD-020B. © 2002 Fairchild Semiconductor Corporation FSAL200 Rev ...
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... Pin Configurations Figure 1. Analog Symbol Control Input(s) X Low High Pin Descriptions Pin Names B1, B2 © 2002 Fairchild Semiconductor Corporation FSAL200 Rev. 1.7.1 Figure 2. Connection Diagram OE Function High Disconnected Low Low Function Switch Enable Select Input Data Ports 2 A=B1 A=B2 www.fairchildsemi.com ...
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... T Operating Temperature Input Rise and Fall Time r f θ Thermal Resistance in Still Sir JA Note: 2. Control input must be held HIGH or LOW and it must not float. © 2002 Fairchild Semiconductor Corporation FSAL200 Rev. 1.7.1 Parameter (1) ( < Parameter (2) Control Input V =2.3V -3.6V CC Control Input V =4 ...
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... B ports). Δ maximum – Flatness is defined as the difference between the maximum and minimum value of on resistance over the specified range of conditions. © 2002 Fairchild Semiconductor Corporation FSAL200 Rev. 1.7.1 Conditions 4.5 to 5.5 3.0 to 3.6 4.5 to 5.5 3.0 to 3.6 0 ≤ V ≤ 5. =10 -30mA 4 ...
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... Capacitance is characterized, but not tested in production. A Symbol Parameter C Control Pin Input Capacitance IN B Port Off Capacitance C IO-B A Port Off Capacitance C Channel On Capacitance ON © 2002 Fairchild Semiconductor Corporation FSAL200 Rev. 1.7.1 . Conditions V (V) CC =3V 4.5 to 5.5 n =1.5V 3.0 to 3.6 n -3V 4 ...
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... AC Loadings and Waveforms © 2002 Fairchild Semiconductor Corporation FSAL200 Rev. 1.7.1 Figure 3. AC Waveforms Figure Loading on off 6 www.fairchildsemi.com ...
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... AC Loadings and Waveforms Figure 6. Off Isolation Figure 8. Crosstalk © 2002 Fairchild Semiconductor Corporation FSAL200 Rev. 1.7.1 (Continued) Figure 5. Charge Injection Test Figure 7. Channel On Capacitance Figure 10. Channel Off Capacitance 7 Figure 9. Bandwidth www.fairchildsemi.com ...
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... Physical Dimensions TOP VIEW SIDE VIEW Figure 11. 16-lead, Quarter Size Outline Package (QSOP), JEDEC MO-137. 0.150” wide Click here for tape and reel specifications, available at: http://www.fairchildsemi.com/products/analog/pdf/qsop16_tr.pdf © 2002 Fairchild Semiconductor Corporation FSAL200 Rev. 1.7.1 LAND PATTERN RECOMMENDATION END VIEW DETAIL A 8 ...
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... MTC16rev4 Figure 12. 16-lead, Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm wide Click here for tape and reel specifications, available at: http://www.fairchildsemi.com/products/analog/pdf/tssop16_tr.pdf © 2002 Fairchild Semiconductor Corporation FSAL200 Rev. 1.7.1 4.55 4.4±0.1 9 5.90 4.45 0.65 1 ...
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... TRADEMARKS The following are registered and unregistered trademarks and service marks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ® ACEx Green FPS™ Build it Now™ Green FPS™ e-Series™ CorePLUS™ GTO™ ...
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... Fairchild Semiconductor Corporation FSAL200 Rev. 1.7.1 11 www.fairchildsemi.com ...