LFXP3E-4TN100C Lattice, LFXP3E-4TN100C Datasheet - Page 145

• Manufacturer Part Number: LFXP3E-4TN100C
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4TN100C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
sysIO Standards Supported in Each Bank
Table 8-3. I/O Standards Supported by Various Banks
LVCMOS Buffer Configurations
All LVCMOS buffers have programmable pull, programmable drive and programmable slew configurations that can
be set in the software.
Programmable Pull-up/Pull-Down/Buskeeper
When configured as LVCMOS or LVTTL, each sysIO buffer has a weak pull-up, a weak pull-down resistor and a
weak buskeeper (bus hold latch) available. Each I/O can independently be configured to have one of these features
or none of them.
Programmable Drive
Each LVCMOS or LVTTL output buffer pin has a programmable drive strength option. This option can be set for
each I/O independently. The drive strength setting available are 2mA, 4mA, 6mA, 8mA, 12mA, 16mA and 20mA.
Actual options available vary by the I/O voltage. The user must consider the maximum allowable current per bank
and the package thermal limit current when selecting the drive strength.
Types of I/O Buffers
Output standards
supported
Inputs
Clock Inputs
PCI Support
LVDS Output Buffers
1. These differential standards are implemented by using complementary LVCMOS driver with external resistor pack.
Description
Single-ended
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18 Class I
SSTL25 Class I, II
SSTL33 Class I, II
HSTL15 Class I, III
HSTL18_I, II, III
SSTL18D Class I,
SSTL25D Class I, II
SSTL33D Class I, II
HSTL15D Class I, III,
HSTL18D Class I, III
PCI33
LVDS25E
LVPECL
BLVDS
RSDS
All Single-ended,
Differential
All Single-ended,
Differential
PCI33 with clamp
1
Banks 0-1
1
Top Side
1
1
Single-ended and Differ-
ential
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18 Class I
SSTL25 Class I, II
SSTL33 Class I, II
HSTL15 Class I, III
HSTL18 Class I, II, III
SSTL18D Class I,
SSTL25D Class I, II
SSTL33D Class I, II
HSTL15D Class I, III
HSTL18D Class I, III
PCI33
LVDS
LVDS25E
LVPECL
BLVDS
RSDS
All Single-ended,
Differential
All Single-ended,
Differential
PCI33 no clamp
LVDS (3.5mA) Buffers
1
Right Side
Banks 2-3
1
1
1
8-5
Single-ended
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18 Class I
SSTL2 Class I, II
SSTL3 Class I, II
HSTL15 Class I, III
HSTL18 Class I, II, III
SSTL18D Class I,
SSTL25D Class I, II,
SSTL33D Class I, II
HSTL15D Class I, III
HSTL18D Class I, III
PCI33
LVDS25E
LVPECL
BLVDS
RSDS
All Single-ended,
Differential
All Single-ended,
Differential
PCI33 with clamp
Bottom Side
1
Banks 4-5
1
1
LatticeECP/EC and LatticeXP
1
sysIO Usage Guide
Single-ended and Differ-
ential
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18 Class I
SSTL2 Class I, II
SSTL3 Class I, II
HSTL15 Class I, III
HSTL18 Class I, II, III
SSTL18D Class I,
SSTL25D Class I, II,
SSTL33D_I, II
HSTL15D Class I, III
HSTL18D Class I, III
PCI33
LVDS
LVDS25E
LVPECL
BLVDS
RSDS
All Single-ended,
Differential
All Single-ended,
Differential
PCI no clamp
LVDS (3.5mA) Buffers
1
Banks 6-7
1
Left Side
1
1