LFXP3E-4TN100C Lattice, LFXP3E-4TN100C Datasheet - Page 235

• Manufacturer Part Number: LFXP3E-4TN100C
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4TN100C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Write Timing Waveforms
Figure 10-17 shows DDR write side data transfer timing for the DQ Data pad and the DQS Strobe Pad. When writ-
ing to the DDR memory device, the DM (Data Mask) and the ADDR/ CMD (Address and Command) signals are
also sent to the memory device along with the data and strobe signals.
Figure 10-17. DDR Write Data Transfer for DQ Data
Design Rules/Guidelines
Listed below are some rules and guidelines to keep in mind when implementing DDR memory interfaces in the Lat-
ticeECP/EC and LatticeXP devices.
• The LatticeECP/EC and LatticeXP devices have dedicated DQ-DQS banks. Please refer to the logical sig-
• There are two DQSDLLs on the device, one for the top half and one for the bottom half. Hence, only one
nal connections of the groups in the LatticeECP/EC and LatticeXP data sheets before locking these pins.
DQSDLL primitive should be instantiated for each half of the device. Since there is only one DQSDLL on
each half of the device, all the DDR memory interfaces on that half of the device should run at the same fre-
quency. Each DQSDLL will generate 90 degree digital delay bits for all the DQS delay blocks on that half of
the device based on the reference clock input to the DLL.
DATAOUT_N
DATAOUT_P
CLK +270
CLK +180
CLKP
CLKN
CLK
DQS
DQ
Notes -
(1) DATAOUT_P and DATAOUT_N are inputs to the DDR output registers.
(2) DQS is generated at 270 degree phase of CLK.
(3) CLKP is generated simular to DQS and CLKN is the inverted CLKP.
(4) DQ is generated at 180 degree phase of CLK.
(5) DQ is center aligned with the DQS strobe signal when it reaches the memory.
P0
N0
P0
N0
10-16
P1
N1
P1
N1
P2
N2
LatticeECP/EC and LatticeXP
P2
N2
DDR Usage Guide