LFXP3E-4TN100C Lattice, LFXP3E-4TN100C Datasheet - Page 147

• Manufacturer Part Number: LFXP3E-4TN100C
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4TN100C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

LatticeECP/EC and LatticeXP
Lattice Semiconductor
sysIO Usage Guide
Figure 7-2. Impedance Matching for a 50¾ Transmission Line with 200¾ Termination (Cont.)
LVCMOS18 8mA
LVCMOS18 4mA
Programmable Slew Rate
Each LVCMOS or LVTTL output buffer pin also has a programmable output slew rate control that can be configured
for either low noise or high-speed performance. Each I/O pin has an individual slew rate control. This allows slew
rate control to be specified on pin-by-pin basis. This slew rate control affects both the rising edges and the falling
edges.
Open Drain Control
All LVCMOS and LVTTL output buffers can be configured to function as open drain outputs. The user can imple-
ment an open drain output by turning on the OPENDRAIN attribute in the software.
The software implements open drain in the LatticeECP/EC and LatticeXP devices by connecting the data and
tristate input of the output buffer. Software will implement open drain using this method for simple output buffers. If
the user wants to assign open drain functionality to a bidirectional I/O, a similar implementation is required in the
HDL design. This can be accomplished by combining the equations for the output enable with the output data. The
function of an open drain output is to drive a high Z when the data to the output buffer is driven high and drive a low
when the data to the output buffer is driven low.
Differential SSTL and HSTL Support
The single-ended driver associated with the complementary ‘C’ pad can optionally be driven by the complement of
the data that drives the single-ended driver associated with the true pad. This allows a pair of single-ended drivers
to be used to drive complementary outputs with the lowest possible skew between the signals. This is used for driv-
ing complementary SSTL and HSTL signals (as required by the differential SSTL and HSTL clock inputs on syn-
chronous DRAM and synchronous SRAM devices respectively). This capability is also used in conjunction with off-
chip resistors to emulate LVPECL and BLVDS output drivers.
PCI Support with Programmable PCICLAMP
Each sysIO buffer can be configured to support PCI33. The buffers on the top and bottom of the device have an
®
optional PCI clamp diode that may optionally be specified in the ispLEVER
design tool.
The programmable PCICLAMP can be turned ON or OFF. This option is available on each I/O independently on the
top and bottom banks.
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