LFXP3E-4TN100C Lattice, LFXP3E-4TN100C Datasheet - Page 309

• Manufacturer Part Number: LFXP3E-4TN100C
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4TN100C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 13-7. Configuration Modes for the LatticeXP
Configuration Options
Several configuration options are available for each CONFIG_MODE.
• When daisy chaining multiple FPGA devices a configuration overflow option is provided. Configuration data over-
• When using a master clock, the master clock frequency can be set.
• A security bit is provided to prevent SRAM or Flash readback.
By setting the proper parameters in the Lattice ispLEVER design software the selected configuration options are
set in the generated bitstream. As the bitstream is loaded into the device the selected configuration options take
effect. These options are described in the following sections.
Bypass Overflow Option
The Bypass overflow option can be used in serial and parallel device daisy chains. When the first device has com-
pleted configuration data download, and the Bypass option preference is selected, data coming into the device
configuration port on the sysCONFIG pins will overflow serially out of DOUT and into the DIN pin of the next slave
serial device. The Bypass option is selected in ispLEVER by right-clicking on Generate Bitstream Data and clicking
on Properties.
In serial configuration mode, once all of the configuration data has been loaded into the first device, the Bypass
option connects the DIN pin to DOUT pin via a bypass register. The bypass register is initialized with a ‘1’ at the
beginning of configuration.
In parallel configuration mode, once all of the configuration data has been loaded into the first device, the Bypass
option causes the data coming from D[0:7] to be serially shifted to DOUT. The serialized data is shifted to DOUT
through the bypass register. D[0] of the byte wide data will be shifted out first followed by D[1], D[2] and so on.
Once the Bypass option starts, the device will remain in Bypass until the wake up sequence completes.
Flow-Though Overflow Option
The Flow-Through overflow option is used in parallel mode only. The Flow-Through option causes the CSON pin to
go low when the FPGA has received all of its configuration data, driving the chip select on the next device in the
daisy chain so that it will start reading configuration data from D[0:7]. The Flow Through Option will also tri-state
Slave Serial (no overload option)
Slave Serial (Bypass ON)
Master Serial (no overload option)
Master Serial (Bypass ON)
Slave Parallel (no overload option)
Slave Parallel (Bypass ON)
Slave Parallel (Flow Through ON)
Self Download Mode (SDM)
ispJTAG (1149.1 interface)
1. CONFIG_MODE can be found in the ispLEVER Preference Editor.
2. CHAIN_MODE can be found in the ispLEVER bitgen options (right-click on Generate Bitstream Data and click on Properties).
3. The ispJTAG interface is always on.
4. If ispJTAG is used exclusively to access the on-chip Flash and SRAM select None, if Slave Parallel is used to access the Flash and/or the
5. The None selection indicates that no dual-purpose pins are reserved for configuration. This is the default.
flow occurs once the first FPGA has completed its download, the remaining data in the configuration storage
device is then output through the first FPGA to subsequent FPGAs. Configuration data overflow is not supported
when using SDM.
SRAM select Slave_Parallel.
Configuration Mode
CFG[1] CFG[0]
X
0
0
0
0
1
1
1
1
3
X
0
0
1
1
0
0
0
1
3
13-10
Slave_Serial
Slave_Serial
Master_Serial
Master_Serial
Slave_Parallel
Slave_Parallel
Slave_Parallel
None/Slave_Parallel
None
5
CONFIG_MODE
LatticeXP sysCONFIG Usage Guide
4
1
Disable
Bypass
Disable
Bypass
Disable
Bypass
Flowthrough
Disable
Chain Mode
2