LFXP3E-4TN100C Lattice, LFXP3E-4TN100C Datasheet - Page 306

• Manufacturer Part Number: LFXP3E-4TN100C
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4TN100C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 13-3. Flash Programming Timing Diagram
Dual-Purpose sysCONFIG Pins
The following is a list of the dual-purpose sysCONFIG pins. These pins are available as general purpose I/O
(GPIO) after configuration. If a dual-purpose pin is to be used both for configuration and as a GPIO, the user must
adhere to the following:
• The I/O type must remain the same. For example, if the pin is a 3.3V CMOS pin (LVCMOS33) during configura-
• The user must select the correct CONFIG_MODE setting and set the PERSISTENT bit to OFF in order to use
• The user is responsible for insuring that no internal or external logic will interfere with device configuration.
Also, if slave parallel configuration mode is not being used then one or both of the parallel port chip selects (CSN,
CS1N) must be high or tri-stated during configuration.
After configuration, these pins, if not used as GPIO, are tri-stated and weakly pulled up.
DIN
DIN (data input) is a dual-purpose input with a weak pull-up. DIN is used for the serial bitstream configurations.
DOUT/CSON
The DOUT/CSON is a dual-purpose output that is used in Chain Mode (daisy chaining). This pin can be used in
serial or parallel modes and has two uses.
For serial and parallel configuration modes, when BYPASS Chain Mode is selected, this pin will become DOUT. In
a serial configuration mode, when the device becomes fully configured, a BYPASS instruction will be executed and
the data on DIN will be presented on the DOUT pin through a bypass register. In this way the serial data is passed
to the next device. In parallel configuration mode the data will be serialized and then presented on DOUT; D[0]
(MSb) will be shifted out first followed by D[1], D[2] and so on to D[7] (LSb).
For parallel configuration mode, when FLOW_THROUGH Chain Mode is selected, this pin will become Chip Select
Out (CSON). In FLOW_THROUGH Chain Mode, when the device is fully configured (the internal DONE bit goes
tion it must remain a 3.3V CMOS pin as GPIO.
the dual-purpose sysCONFIG pins as GPIO after configuration. These settings can be found in the ispLEVER
Design Planner (formerly called the Preference Editor).
PROGRAMN
WRITEN
D[0:7]
BUSY
CCLK
CS1N
INITN
CSN
LOW to select Direct Programming. High to select Background Programming.
13-7
LatticeXP sysCONFIG Usage Guide
Drive to LOW if error happens
FLASH to SRAM upload happens if DONE
fuse is programmed and CFG[1:0] are high.