LFXP3E-4TN100C Lattice, LFXP3E-4TN100C Datasheet - Page 363

• Manufacturer Part Number: LFXP3E-4TN100C
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4TN100C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 18-1. Read Operation Timing Arcs
Set-up Time Calculation for the Data Input (Max. Case)
The DDR Controller IP core uses the positive edge of pll_nclk to latch in the data.
Table 18-1 timing arcs are used to calculate the following:
Therefore:
Isolating the board delays, we get:
Hold Time Calculation for the Data Input (Min. Case)
As shown in Figure 18-2, the min data is available at DDR output pins after t
ddr_clk. Since t
board delay (t
t
t
t
t
t
t
t
t
t
t
t
t
t
1. t
CK
DDR_CLK
DDR_CLK
BDC
AC(MAX)
AC(MIN)
BDD
PD
FDS
FDH
SKEW
FPGA_CLK
FPGA_CLK
FPGA_CLK,
Symbol
Max. delay of clock to ddr_dq_in flops = t
Max. delay of DDR read data to ddr_dq_in flops = t
To meet set-up time at ddr_dq_in flops, Clock Delay - Data Delay > 0
t
(t
(t
(t
Min. Delay of DDR read Data = t
(max)
(min)
FPGA_CLK
(max)
(min)
BDD
BDD
BDD
t
DDR_CLK,
+ t
+ t
+ t
BDD
BDC
BDC
BDC
) and propagation delay from FPGA input pad to the flip-flop input pin (t
Clock period of ddr_clk
Delay from the CLK input of the FPGA to the ddr_clk pad including Feedback
compensation (Clock Path Delay - Feedback Path).
Delay from the CLK input of the FPGA to the ddr_clk pad including Feedback
compensation (Clock Path Delay - Feedback Path).
Board delay of ddr_clk from FPGA to DDR SDRAM.
Time from the rising edge of ddr_clk after which the data is available at DDR 
output pins (max.).
Time from the rising edge of ddr_clk after which the data is available at DDR 
output pins (min.).
Board delay from DDR SDRAM data pad to the FPGA ddr_dq pad.
Propagation delay from FPGA input pad to the ddr_dq_in flip-flop input pin (Data
Path Delay).
Set-up time required by the ddr_dq_in flip-flop (INREG_SET).
Hold time required by the ddr_dq_in flip-flop (INREG_HLD).
Skew of the PLL.
Delay from the CLK input of the FPGA to the ddr_dq_in flip-flop clock input includ-
ing feedback compensation (Clock Out Path Delay - Feedback Path).
Delay from the CLK input of the FPGA to the ddr_dq_in flip-flop clock input includ-
ing feedback compensation (Clock Out Path Delay - Feedback Path).
(max) + (t
AC
t
PD
) < t
) < 3.75 - 0.3 - 3.195 - 2.47 + 2.935 - 0.75 - 0.0
) < -0.03 ns
(min) is generally a negative number, data appears before the rising edge. This data will incur
and t
FPGA_CLK
FDS
CK
can be easily obtained from the PNR time reports.
* 1/2) - t
(max) + (t
SKEW
DDR_CLK
CK
- t
* 1/2) - t
FDS
(min) + t
Description
- t
FPGA_CLK
DDR_CLK
SKEW
18-3
BDC
- t
(max) - t
(max) + (t
FDS
+ t
DDR_CLK
AC
for the DDR SDRAM Controller IP Core
- t
DDR_CLK
(min) + t
BDC
(max) + t
CK
- t
* 1/2) - t
AC
(max) - t
BDD
(max) - t
AC
BDC
+ t
(min) time from the rising edge of
SKEW
PD
Board Timing Guidelines
+ t
AC
AC
BDD
(max) - t
- t
(max) + t
FDS
PD
- t
).
PD
PD
DDR-NP on ORCA 4
> 0
BDD
Example:
-1.609ns
3.195ns
2.935ns
1.239ns
-0.75ns
0.75ns
1.138
+ t
0.0ns
7.5ns
0.3ns
2.47
—
—
PD
1
1
1
1
1
1
1