LH28F008SAHT-T9 Sharp Electronics, LH28F008SAHT-T9 Datasheet - Page 11

• Manufacturer Part Number: LH28F008SAHT-T9
• Manufacturer: Sharp Electronics

Specifications of LH28F008SAHT-T9

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 11.4 to 12.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Compliant

3.
The LH28F008SAHT-T9 includes on-chip write automation
to manage write and erase functions. The Write State Ma-
chine allows for: 100% TTL-level control inputs; fixed power
supplies during block erasure and byte write; and minimal
processor overhead with SRAM-like interface timings.
After initial device powerup, or after return from deep
p o w e r d o w n m o d e ( s e e B u s O p e r a t i o n s ) , t h e
LH28F008SAHT-T9 functions as a read-only memory. Ma-
nipulation of external memory-control pins allow array read,
standby and output disable operations. Both Status Regis-
ter and intelligent identifiers can also be accessed through
the Command User Interface when V
This same subset of operations is also available when high
voltage is applied to the V
V
the device. All functions associated with altering memory
contents — byte write, block erase, status and intelligent
identifier — are accessed via the Command User Interface
and verified thru the Status Register.
Commands are written using standard microprocessor write
timings. Command User Interface contents serve as input
to the WSM, which controls the block erase and byte write
circuitry. Write cycles also internally latch addresses and
data needed for byte write or block erase operations. With
the appropriate command written to the register, standard
microprocessor read timings output array data, access the
intelligent identifier codes, or output byte write and block
erase status for verification.
Interface software to initiate and poll progress of internal
byte write and block erase can be stored in any of the
LH28F008SAHT-T9 blocks. This code is copied to, and ex-
ecuted from, system RAM during actual flash memory up-
date. After successful completion of byte write and/or block
erase, code/data reads from the LH28F008SAHT-T9 are
again possible via the Read Array command. Erase sus-
pend/resume capability allows system software to suspend
block erase to read data and execute code from any other
block.
PP
enables successful block erasure and byte writing of
PRINCIPLES OF OPERATION
PP
pin. In addition, high voltage on
PP
=V
PPL
.
LHF08ST9
Command User Interface and Write Automation
An on-chip state machine controls block erase and byte
write, freeing the system processor for other tasks. After re-
ceiving the Erase Setup and Erase Confirm commands, the
state machine controls block pre-conditioning and erase,
returning progress via the Status Register and RY/BY#
output. Byte write is similarly controlled, after destination
address and expected data are supplied. The program and
erase algorithms of past standard Flash memories are now
regulated by the state machine, including pulse repetition
where required and internal verification and margining of
data.
FFFFF
F0000
EFFFF
E0000
DFFFF
D0000
CFFFF
C0000
BFFFF
B0000
AFFFF
A0000
9FFFF
90000
8FFFF
80000
7FFFF
70000
6FFFF
60000
5FFFF
50000
4FFFF
40000
3FFFF
30000
2FFFF
20000
1FFFF
10000
0FFFF
00000
Figure 4. Memory Map
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
8