LH28F008SAHT-T9 Sharp Electronics, LH28F008SAHT-T9 Datasheet - Page 15

• Manufacturer Part Number: LH28F008SAHT-T9
• Manufacturer: Sharp Electronics

Specifications of LH28F008SAHT-T9

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 11.4 to 12.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Compliant

Read Status Register Command
The LH28F008SAHT-T9 contains a Status Register which
may be read to determine when a byte write or block erase
operation is complete, and whether that operation com-
pleted successfully. The Status Register may be read at
any time by writing the Read Status Register command
(70H) to the Command User Interface. After writing this
command, all subsequent read operations output data from
the Status Register, until another valid command is written
to the Command User Interface. The contents of the Status
Register are latched on the falling edge of OE# or CE#,
whichever occurs last in the read cycle. OE# or CE# must
be toggled to V
Register latch. The Read Status Register command func-
tions when V
Clear Status Register Command
The Erase Status and Byte Write Status bits are set to "1"s
by the Write State Machine and can only be reset by the
Clear Status Register Command. These bits indicate vari-
ous failure conditions (see Table 4). By allowing system
software to control the resetting of these bits, several opera-
tions may be performed (such as cumulatively writing sev-
eral bytes or erasing multiple blocks in sequence). The Sta-
tus Register may then be polled to determine if an error oc-
curred during that sequence. This adds flexibility to the way
the device may be used.
Additionally, the V
system software before further byte writes or block erases
are attempted. To clear the Status Register, the Clear Sta-
tus Register command (50H) is written to the Command
User Interface. The Clear Status Register command is func-
tional when V
Erase Setup/Erase Confirm Commands
Erase is executed one block at a time, initiated by a two-
cycle command sequence. An Erase Setup command
(20H) is first written to the Command User Interface, fol-
lowed by the Erase Confirm command (D0H). These com-
mands require both appropriate sequencing and an ad-
dress within the block to be erased to FFH. Block precondi-
tioning, erase and verify are all handled internally by the
Write State Machine, invisible to the system. After the two-
c o m m a n d e r a s e s e q u e n c e i s w r i t t e n t o i t , t h e
PP
PP
IH
=V
=V
before further reads to update the Status
PPL
PPL
PP
Status bit (SR.3) MUST be reset by
or V
or V
PPH
PPH
.
.
LHF08ST9
LH28F008SAHT-T9 automatically outputs Status Register
data when read (see Figure 6; Block Erase Flowchart). The
CPU can detect the completion of the erase event by ana-
lyzing the output of the RY/BY# pin, or the WSM Status bit
of the Status Register.
When erase is completed, the Erase Status bit should be
checked. If erase error is detected, the Status Register
should be cleared. The Command User Interface remains in
Read Status Register mode until further commands are is-
sued to it.
This two-step sequence of set-up followed by execution en-
sures that memory contents are not accidentally erased.
Also, reliable block erasure can only occur when
V
contents are protected against erasure. If block erase is
attempted while V
"1". Erase attempts while V
spurious results and should not be attempted.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows block erase interrup-
tion in order to read data from another block of memory.
Once the erase process starts, writing the Erase Suspend
command (B0H) to the Command User Interface requests
that the WSM suspend the erase sequence at a predeter-
mined point in the erase algorithm. The LH28F008SAHT-T9
continues to output Status Register data when read, after
the Erase Suspend command is written to it. Polling the
WSM Status and Erase Suspend Status bits will determine
when the erase operation has been suspended (both will be
set to "1"). RY/BY# will also transition to V
At this point, a Read Array command can be written to the
Command User Interface to read data from blocks other
than that which is suspended. The only other valid com-
mands at this time are Read Status Register (70H) and
Erase Resume (D0H), at which time the WSM will continue
with the erase process. The Erase Suspend Status and
WSM Status bits of the Status Register will be automatically
cleared and RY/BY# will return to V
sume command is written to it, the LH28F008SAHT-T9 au-
tomatically outputs Status Register data when read (see
Figure 7; Erase Suspend/Resume Flowchart). V
main at V
pend.
PP
=V
PPH
PPH
. In the absence of this high voltage, memory
while the LH28F008SAHT-T9 is in Erase Sus-
PP
=V
PPL
, the V
PPL
PP
OL
<V
Status bit will be set to
. After the Erase Re-
PP
<V
OH
PPH
.
PP
produce
must re-
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