LH28F008SAHT-T9 Sharp Electronics, LH28F008SAHT-T9 Datasheet - Page 17

• Manufacturer Part Number: LH28F008SAHT-T9
• Manufacturer: Sharp Electronics

Specifications of LH28F008SAHT-T9

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 11.4 to 12.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Compliant

RY/BY# and Byte Write/Block Erase Polling
RY/BY# is a full CMOS output that provides a hardware
method of detecting byte write and block erase completion.
It transitions low time t
sequence is written to the LH28F008SAHT-T9, and returns
to V
algorithm.
FULL STATUS CHECK PROCEDURE
OH
Status Register Data
Read (See Above)
when the WSM has finished executing the internal
Successful
Byte Write
SR.3=0
SR.4=0
?
?
YES
YES
Write 40H (10H),
Check if Desired
Address/Data
Byte Address
Write Byte
Full Status
Completed
Byte Write
NO
NO
Ready?
WHRL
WSM
Start
YES
after a write or erase command
NO
V
Byte Write
PP
Error
Error
Range
Figure 5. Automated Byte Write Flowchart
LHF08ST9
Standby/Read
Repeat for subsequent bytes
Full status check can be done after each byte or after a
sequence of bytes
Write FFH after the last byte write operation to reset the
device to Read Array Mode
Operation
Operation
SR.3 MUST be cleared, if set during a byte write attempt,
before further attempts are allowed by the Write State
Machine.
SR.4 is only cleared by the Clear Status Register Command,
in cases where multiple bytes are written before full status is
checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
RY/BY# can be connected to the interrupt input of the sys-
tem CPU or controller. It is active at all times, not tristated if
the LH28F008SAHT-T9 CE# or OE# inputs are brought to
V
pend or deep powerdown modes.
Optional
Standby
Standby
IH
Read
Write
Write
Bus
Bus
. RY/BY# is also V
Command
Byte Write
Byte Write
Command
Setup
OH
when the device is in Erase Sus-
CPU may already have read
Status Register data in WSM
Ready polling above
Check SR.3
1=V
Check SR.4
1=Byte Write Error
Data=40H(10H)
Address=Byte to be written
Data to be written
Address=Byte to be written
Check RY/BY#
V
Read Status Register
Check SR.7
1=Ready, 0=Busy
Toggle OE# or CE# to
update Status Register
OH
PP
=Ready, V
Low Detect
Comments
Comments
or
OL
=Busy
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