LH28F008SAHT-T9 Sharp Electronics, LH28F008SAHT-T9 Datasheet - Page 12

LH28F008SAHT-T9

Manufacturer Part Number
LH28F008SAHT-T9
Description
Manufacturer
Sharp Electronics
Datasheet

Specifications of LH28F008SAHT-T9

Cell Type
NOR
Density
8Mb
Access Time (max)
90ns
Interface Type
Parallel
Boot Type
Not Required
Address Bus
20b
Operating Supply Voltage (typ)
5V
Operating Temp Range
-40C to 85C
Package Type
TSOP
Program/erase Volt (typ)
11.4 to 12.6V
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Word Size
8b
Number Of Words
1M
Supply Current
50mA
Mounting
Surface Mount
Pin Count
40
Lead Free Status / Rohs Status
Compliant
Data Protection
Depending on the application, the system designer may
choose to make the V
only when memory byte writes/block erases are required) or
hardwired to V
cannot be altered. The LH28F008SAHT-T9 Command User
Interface architecture provides protection from unwanted
byte write or block erase operations even when high voltage
is applied to V
whenever V
when RP# is at V
dates either design practice and encourages optimization of
the processor-memory interface.
The two-step byte write/block erase Command User Inter-
face write sequence provides additional software write pro-
tection.
4.
Flash memory reads, erases and writes in-system via the
local CPU. All bus cycles to or from the flash memory con-
form to standard microprocessor bus cycles.
Read
The LH28F008SAHT-T9 has three read modes. The
memory can be read from any of its blocks, and information
can be read from the intelligent identifier or Status Register.
V
NOTES:
1. Refer to DC Characteristics. When V
2. X can be V
3. RY/BY# is V
4. Command writes involving block erase or byte write are only successfully executed when V
5. Refer to Table 3 for valid D
6. Don't use the timing both OE# and WE# are V
PP
Read
Output Disable
Standby
Deep PowerDown
Intelligent Identifier (Mfr)
Intelligent Identifier (Device)
Write
not busy, in Erase Suspend mode or deep powerdown mode.
can be at either V
BUS OPERATION
CC
IL
OL
or V
Mode
PP
is below the write lockout voltage V
PPH
when the Write State Machine is executing internal block erase or byte write algorithms. It is V
. Additionally, all functions are disabled
IH
IL
. When V
for control pins and addresses, and V
. The LH28F008SAHT-T9 accommo-
PP
PPL
power supply switchable (available
or V
I
N
during a write operation.
PP
PPH
=V
.
PPL
PP
=V
Notes
4,5,6
, memory contents
PPL
6
6
6
, memory contents can be read but not written or erased.
IL
.
Table 2. Bus Operations
RP#
V
V
V
V
V
V
V
IH
IH
IH
IH
IH
IH
IL
LKO
PPL
LHF08ST9
, or
or V
CE#
V
V
V
V
V
V
X
PPH
IH
IL
IL
IL
IL
IL
The first task is to write the appropriate read mode com-
mand to the Command User Interface (array, intelligent
identifier, or Status Register). The LH28F008SAHT-T9 au-
tomatically resets to Read Array mode upon initial device
powerup or after exit from deep powerdown. The
LH28F008SAHT-T9 has four control pins, two of which
must be logically active to obtain data at the outputs. Chip
Enable (CE#) is the device selection control, and when
active enables the selected memory device. Output Enable
(OE#) is the data input/output (DQ
and when active drives data from the selected memory onto
the I/O bus. RP# and WE# must also be at V
illustrates read bus cycle waveforms.
Output Disable
With OE# at a logic-high level (V
disabled. Output pins (DQ
pedance state.
Standby
CE# at a logic-high level (V
T9 in standby mode. Standby operation disables much of
the LH28F008SA’s circuitry and substantially reduces de-
vice power consumption. The outputs (DQ
placed in a high-impedence state independent of the status
of OE#. If the LH28F008SAHT-T9 is deselected during
block erase or byte write, the device will continue
functioning and consuming normal active power until the
operation completes.
for V
OE#
V
V
V
V
V
X
X
PP
IH
IH
IL
IL
IL
. See DC Characteristics for V
(1,2)
WE#
V
V
V
V
V
X
X
IH
IH
IH
IH
IL
V
V
A
PP
X
X
X
X
X
IH
IL
0
=V
PPH
0
IH
-DQ
V
.
) places the LH28F008SAHT-
X
X
X
X
X
X
X
PP
7
IH
) are placed in a high-im-
PPL
0
), the device outputs are
-DQ
High Z
High Z
High Z
OH
DQ
D
and V
A2H
89H
D
OUT
7
when the WSM is
) direction control,
IN
0-7
PPH
voltages.
IH
0
RY/BY#
-DQ
. Figure 8
V
V
V
X
X
X
X
OH
OH
OH
7
) are
(3)
9

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