LH28F008SAHT-T9 Sharp Electronics, LH28F008SAHT-T9 Datasheet - Page 16

• Manufacturer Part Number: LH28F008SAHT-T9
• Manufacturer: Sharp Electronics

Specifications of LH28F008SAHT-T9

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 11.4 to 12.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Compliant

Byte Write Setup/Write Commands
Byte write is executed by a two-command sequence. The
Byte Write Setup command (40H or 10H) is written to the
Command User Interface, followed by a second write
specifying the address and data (latched on the rising edge
of WE#) to be written. The WSM then takes over, controlling
the byte write and write verify algorithms internally. After the
two-command byte write sequence is written to it, the
LH28F008SAHT-T9 automatically outputs Status Register
data when read (see Figure 5; Byte Write Flowchart). The
CPU can detect the completion of the byte write event by
analyzing the output of the RY/BY# pin, or the WSM Status
bit of the Status Register. Only the Read Status Register
command is valid while byte write is active.
When byte write is complete, the Byte Write Status bit
should be checked. If byte write error is detected, the Status
Register should be cleared. The internal WSM verify only
detects errors for "1"s that do not successfully write to "0"s.
The Command User Interface remains in Read Status Reg-
ister mode until further commands are issued to it. If byte
write is attempted while V
set to "1". Byte write attempts while V
produce spurious results and should not be attempted.
6.
CYCLING
The LH28F008SAHT-T9 is designed for 100,000 byte write/
block erase cycles on each of the sixteen 64K-byte blocks.
Low electric fields, advanced oxides and minimal oxide
area per cell subjected to the tunneling electric field com-
bine to greatly reduce oxide stress and the probability of
failure. A 20M-byte solid-state drive using an array of
LH28F008SA’s has a MTBF (Mean Time Between Failure)
of 33.3 million hours
equivalent rotating disk technology.
7.
The LH28F008SAHT-T9 integrates the Quick-Pulse pro-
gramming algorithm using the Command User Interface,
Status Register and Write State Machine (WSM). On-chip
integration dramatically simplifies system software and pro-
vides processor interface timings to the Command User In-
terface and Status Register. WSM operation, internal verify
and V
via the RY/BY# output and appropriate Status Register bits.
Figure 5 shows a system software flowchart for device byte
write. The entire sequence is performed with V
(1) Assumptions: 10K-byte file written every 10 minutes. (20M-byte array)/(10K-byte file) = 2,000 file writes before erase required.
(2000 files writes/erase) x (100,000 cycles per LH28F008SAHT-T9 block) = 200 million file writes.
(200 x 10
EXTENDED BLOCK ERASE/BYTE WRITE
AUTOMATED BYTE WRITE
PP
6
file writes) x (10 min/write) x (1 hr/60 min) = 33.3 x 10
high voltage presence are monitored and reported
(1)
, over 600 times more reliable than
PP
=V
PPL
, the V
PP
PPL
Status bit will be
<V
PP
PP
at V
6
MTBF.
<V
LHF08ST9
PPH
PPH
.
Byte write abort occurs when RP# transitions to V
drops to V
partially written at the location where byte write was
aborted. Block erasure, or a repeat of byte write, is required
to initialize this data to a known value.
8.
As above, the Quick-Erase algorithm is now implemented
internally, including all preconditioning of block data. WSM
operation, erase success and V
are monitored and reported through RY/BY# and the Status
Register. Additionally, if a command other than Erase Con-
firm is written to the device following Erase Setup, both the
Erase Status and Byte Write Status bits will be set to "1"s.
When issuing the Erase Setup and Erase Confirm com-
mands, they should be written to an address within the ad-
dress range of the block to be erased. Figure 6 shows a
system software flowchart for block erase.
Erase typically takes 1.6s per block. The Erase Suspend/
Erase Resume command sequence allows suspension of
this erase operation to read data from a block other than
that in which erase is being performed. A system software
flowchart is shown in Figure 7.
The entire sequence is performed with V
occurs when RP# transitions to V
while erase is in progress. Block data is partially erased by
this operation, and a repeat of erase is required to obtain a
fully erased block.
9.
Three-Line Output Control
The LH28F008SAHT-T9 will often be used in large memory
arrays. SHARP provides three control inputs to
accommodate multiple memory connections. Three-line
control provides for:
a) lowest possible memory power dissipation
b) complete assurance that data bus contention will not oc-
To efficiently use these control inputs, an address decoder
should enable CE#, while OE# should be connected to all
memory devices and the system’s READ# control line. This
assures that only selected memory devices have active out-
puts while deselected memory devices are in Standby
Mode. Finally, RP# should either be tied to the system
RESET#, or connected to V
cur
AUTOMATED BLOCK ERASE
DESIGN CONSIDERATIONS
PPL
. Although the WSM is halted, byte data is
CC
if unused.
PP
IL
high voltage presence
or V
PP
PP
at V
falls to V
PPH
IL
, or V
. Abort
PPL
PP
,
13