CY7C68013-56LFC Cypress Semiconductor Corp, CY7C68013-56LFC Datasheet - Page 10

• Manufacturer Part Number: CY7C68013-56LFC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C68013-56LFC

• Cpu Family: FX2LP
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 48MHz
• Interface Type: USB
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 24
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Package Type: QFN EP
• Lead Free Status / Rohs Status: Not Compliant

3.16
FX2 provides two identical autopointers. They are similar to
the internal 8051 data pointers, but with an additional feature:
they can optionally increment a pointer address after every
memory access. This capability is available to and from both
internal and external RAM. The autopointers are available in
external FX2 registers, under control of a mode bit (AUTOP-
TRSETUP.0). Using the external FX2 autopointer access (at
0xE67B – 0xE67C) allows the autopointer to access all RAM,
internal and external to the part. Also, the autopointers can
point to any FX2 register or endpoint buffer space. When
autopointer access to external memory is enabled, location
0xE67B and 0xE67C in XDATA and PDATA space cannot be
used.
3.17
FX2 has one I
controllers, one that automatically operates at boot time to
load VID/PID/DID and configuration information, and another
that the 8051, once running, uses to control external I
compatible devices. The I
master mode only.
3.17.1
The I
2.2-kΩ pull-up resistors. External EEPROM device address
pins must be configured properly. See Table 3-7 for config-
uring the device address pins.
Table 3-7. Strap Boot EEPROM Address Lines to These
Values
Note:
Document #: 38-08012 Rev. *F
4.
16
128
256
4K
8K
Bytes
This EEPROM does not have address pins.
2
C-compatible pins SCL and SDA must have external
Autopointer Access
I
I
2
2
C-compatible Port Pins
C-compatible Controller
24LC00
24LC01
24LC02
24LC32
24LC64
Example EEPROM
2
C-compatible port that is driven by two internal
[4]
2
C-compatible port operates in
N/A
A2
0
0
0
0
N/A
A1
0
0
0
0
N/A
A0
0
0
1
1
2
C-
3.17.2
At power-on reset the I
load the VID/PID/DID/a configuration byte and up to eight
kbytes of program/data. The available RAM spaces are eight
kbytes
0xE000–0xE1FF. The 8051 will be in reset. I
interface boot loads only occur after power-on reset.
3.17.3
The 8051 can control peripherals connected to the I
compatible bus using the I2CTL and I2DAT registers. FX2
provides I
compatible slave.
4.0
Figure 4-1 identifies all signals for the four package types. The
following pages illustrate the individual pin diagrams, plus a
combination diagram showing which of the full set of signals
are available in the 128-, 100-, and 56-pin packages.
The 56-pin package is the lowest-cost version. The signals on
the left edge of the 56-pin package in Figure 4-1 are common
to all versions in the FX2 family. Three modes are available in
all package versions: Port, GPIF master, and Slave FIFO.
These modes define the signals on the right edge of the
diagram. The 8051 selects the interface mode using the
IFCONFIG[1:0] register bits. Port mode is the power-on default
configuration.
The 100-pin package adds functionality to the 56-pin package
by adding these pins:
The 128-pin package is the full version, adding the 8051
address and data buses plus control signals. Note that two of
the required signals, RD# and WR#, are present in the 100-pin
version. In the 100-pin and 128-pin versions, an 8051 control
bit can be set to pulse the RD# and WR# pins when the 8051
reads from/writes to PORTC.
• PORTC or alternate GPIFADR[7...0] address signals
• PORTE or alternate GPIFADR8 address signals and 7 more
• Three GPIF Control signals
• Four GPIF Ready signals
• Nine 8051 signals (two USARTs, three timer inputs,
• BKPT, RD#, WR#
8051 signals
INT4,and INT5#)
I
I
from
2
2
2
Pin Assignments
C-compatible Interface General Purpose Access
C-compatible Interface Boot Load Access
C compatible master control only, it is never an I
0x0000–0x1FFF
2
C-compatible interface boot loader will
and
CY7C68013
512
2
Page 10 of 48
C-compatible
bytes
from
2
2
C-
C-