CY7C68013-56LFC Cypress Semiconductor Corp, CY7C68013-56LFC Datasheet - Page 5

• Manufacturer Part Number: CY7C68013-56LFC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C68013-56LFC

• Cpu Family: FX2LP
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 48MHz
• Interface Type: USB
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 24
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Package Type: QFN EP
• Lead Free Status / Rohs Status: Not Compliant

Table 3-4. Individual FIFO/GPIF Interrupt Sources
3.8.3
Just as the USB Interrupt is shared among 27 individual USB-
interrupt sources, the FIFO/GPIF interrupt is shared among 14
individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, like
the USB Interrupt, can employ autovectoring. Table 3-4 shows
the priority and INT4VEC values for the 14 FIFO/GPIF
interrupt sources.
If Autovectoring is enabled (AV4EN = 1 in the INTSETUP
register), the FX2 substitutes its INT4VEC byte. Therefore, if
the high byte (“page”) of a jump-table address is preloaded at
location 0x0054, the automatically-inserted INT4VEC byte at
0x0055 will direct the jump to the correct address out of the 14
addresses within the page. When the ISR occurs, the FX2
pushes the program counter onto its stack then jumps to
address 0x0053, where it expects to find a “jump” instruction
to the ISR Interrupt service routine.
3.9
3.9.1
An input pin (RESET#) resets the chip. This pin has hysteresis
and is active LOW. The internal PLL stabilizes approximately
200 µs after V
network (R = 100k, C = 0.1 µF) is used to provide the RESET#
signal.
3.9.2
The 8051 puts itself and the rest of the chip into a power-down
mode by setting PCON.0 = 1. This stops the oscillator and
PLL. When WAKEUP is asserted by external logic, the oscil-
lator restarts and after the PLL stabilizes, and the 8051
receives a wakeup interrupt. This applies whether or not FX2
is connected to the USB.
The FX2 exits the power down (USB suspend) state using one
of the following methods:
Document #: 38-08012 Rev. *F
• USB bus signals resume
• External logic asserts the WAKEUP pin
• External logic asserts the PA3/WU2 pin.
Priority
10
11
12
13
14
1
2
3
4
5
6
7
8
9
FIFO/GPIF Interrupt (INT4)
Reset and Wakeup
Reset Pin
Wakeup Pins
CC
has reached 3.3V. Typically, an external RC
INT4VEC Value
AC
8C
9C
A0
A4
80
88
90
94
98
A8
B0
B4
84
GPIFDONE
GPIFWF
Source
EP2PF
EP4PF
EP6PF
EP8PF
EP2EF
EP4EF
EP6EF
EP8EF
EP2FF
EP4FF
EP6FF
EP8FF
Endpoint 2 Programmable Flag
Endpoint 4 Programmable Flag
Endpoint 6 Programmable Flag
Endpoint 8 Programmable Flag
Endpoint 2 Empty Flag
Endpoint 4 Empty Flag
Endpoint 6 Empty Flag
Endpoint 8 Empty Flag
Endpoint 2 Full Flag
Endpoint 4 Full Flag
Endpoint 6 Full Flag
Endpoint 8 Full Flag
GPIF Operation Complete
GPIF Waveform
The second wakeup pin, WU2, can also be configured as a
general purpose I/O pin. This allows a simple external R-C
network to be used as a periodic wakeup source.
3.10
3.10.1
The FX2 has eight kbytes of internal program/data RAM,
where PSEN#/RD# signals are internally ORed to allow the
8051 to access it as both program and data memory. No USB
control registers appear in this space.
Two memory maps are shown in the following diagrams:
Figure 3-1 Internal Code Memory, EA = 0
Figure 3-2 External Code Memory, EA = 1.
3.10.2
This mode implements the internal eight-kbyte block of RAM
(starting at 0) as combined code and data memory. When
external RAM or ROM is added, the external read and write
strobes are suppressed for memory spaces that exist inside
the chip. This allows the user to connect a 64-kbyte memory
without requiring address decodes to keep clear of internal
memory spaces.
Only the internal eight kbytes and scratch pad 0.5 kbytes
RAM spaces have the following access:
3.10.3
The bottom eight kbytes of program memory is external, and
therefore the bottom eight kbytes of internal RAM is accessible
only as data memory.
• USB download
• USB upload
• Setup data pointer
• I
2
C-compatible interface boot load.
Program/Data RAM
Size
Internal Code Memory, EA = 0
External Code Memory, EA = 1
Notes
CY7C68013
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