CY7C68013-56LFC Cypress Semiconductor Corp, CY7C68013-56LFC Datasheet - Page 38

• Manufacturer Part Number: CY7C68013-56LFC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C68013-56LFC

• Cpu Family: FX2LP
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 48MHz
• Interface Type: USB
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 24
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Package Type: QFN EP
• Lead Free Status / Rohs Status: Not Compliant

9.11
Table 9-13. Slave FIFO Asynchronous Packet End Strobe Parameters
9.12
Table 9-14. Slave FIFO Output Enable Parameters
9.13
Table 9-15. Slave FIFO Address to Flags/Data Parameters
Document #: 38-08012 Rev. *F
t
t
t
t
t
t
t
PEpwl
PWpwh
XFLG
OEon
OEoff
XFLG
XFD
Parameter
Parameter
Parameter
Slave FIFO Asynchronous Packet End Strobe
Slave FIFO Output Enable
Slave FIFO Address to Flags/Data
PKTEND Pulse Width LOW
PKTEND Pulse Width HIGH
PKTEND to FLAGS Output Propagation Delay
SLOE Assert to FIFO DATA Output
SLOE Deassert to FIFO DATA Hold
FIFOADR[1:0] to FLAGS Output Propagation Delay
FIFOADR[1:0] to FIFODATA Output Propagation Delay
Figure 9-11. Slave FIFO Asynchronous Packet End Strobe Timing Diagram
FIFOADR [1.0]
Figure 9-13. Slave FIFO Address to Flags/Data Timing Diagram
Figure 9-12. Slave FIFO Output Enable Timing Diagram
DATA
SLOE
FLAGS
PKTEND
DATA
FLAGS
Description
Description
Description
t
t
PEpwl
t
OEon
XFLG
t
XFLG
t
XFD
N
N+1
[16]
t
PEpwh
t
OEoff
Min.
Min.
Min.
50
50
[13]
[13]
Max.
Max.
Max.
10.5
10.5
10.7
14.3
115
[13]
CY7C68013
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Unit
Unit
Unit
ns
ns
ns
ns
ns
ns
ns