CY7C68013-56LFC Cypress Semiconductor Corp, CY7C68013-56LFC Datasheet - Page 40

• Manufacturer Part Number: CY7C68013-56LFC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C68013-56LFC

• Cpu Family: FX2LP
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 48MHz
• Interface Type: USB
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 24
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Package Type: QFN EP
• Lead Free Status / Rohs Status: Not Compliant

9.16
9.16.1
Figure 9-16 shows the timing relationship of the SLAVE FIFO
signals during a synchronous FIFO read using IFCLK as the
synchronizing clock. The diagram illustrates a single read
followed by a burst read.
Document #: 38-08012 Rev. *F
FLAGS
FIFOADR
FIFO POINTER
• At t = 0 the FIFO address is stable and the signal SLCS is
• At = 1, SLOE is asserted. SLOE is an output enable only,
• At t = 2, SLRD is asserted. SLRD must meet the setup time
IFCLK
SLRD
SLCS
DATA
FIFO DATA BUS
SLOE
asserted (SLCS may be tied low in some applications).
Note: t
is running at 48 MHz, the FIFO address set-up time is more
than one IFCLK cycle.
whose sole function is to drive the data bus. The data that
is driven on the bus is the data that the internal FIFO pointer
is currently pointing to. In this example it is the first data
value in the FIFO. Note: the data is pre-fetched and is driven
on the bus when SLOE is asserted.
of t
edge of the IFCLK) and maintain a minimum hold time of
t
SLRD signal). If the SLCS signal is used, it must be asserted
RDH
SRD
(time from the IFCLK edge to the de-assertion of the
Sequence Diagram
Single and Burst Synchronous Read Example
SFA
(time from asserting the SLRD signal to the rising
has a minimum of 25 ns. This means when IFCLK
Not Driven
t=0
IFCLK
N
t=1
SLOE
t
SFA
Figure 9-16. Slave FIFO Synchronous Read Sequence and Timing Diagram
Figure 9-17. Slave FIFO Synchronous Sequence of Events Diagram
t
OEon
Data Driven: N
t=2
Driven: N
t
SRD
IFCLK
N
t
IFCLK
t
XFD
t=3
t
RDH
SLRD
t
XFLG
t
OEoff
N+1
t=4
t
N+1
FAH
IFCLK
N+1
SLOE
SLRD
Not Driven
IFCLK
t
T=0
N+1
SFA
The same sequence of events are shown for a burst read and
are marked with the time indicators of T = 0 through 5. Note:
For the burst mode, the SLRD and SLOE are left asserted
during the entire duration of the read. In the burst read mode,
when SLOE is asserted, data indexed by the FIFO pointer is
on the data bus. During the first read cycle, on the rising edge
of the clock the FIFO pointer is updated and increments to
point to address N+1. For each subsequent rising edge of
IFCLK, while the SLRD is asserted, the FIFO pointer is incre-
mented and the next data value is placed on the data bus.
t
OEon
SLOE
• The FIFO pointer is updated on the rising edge of the IFCLK,
with SLRD, or before SLRD is asserted (i.e. the SLCS and
SLRD signals must both be asserted to start a valid read
condition).
while SLRD is asserted. This starts the propagation of data
from the newly addressed location to the data bus. After a
propagation delay of t
of IFCLK) the new data value is present. N is the first data
value read from the FIFO. In order to have data on the FIFO
data bus, SLOE MUST also be asserted.
T=2
>= t
T=1
N+1
IFCLK
N+1
SRD
N+1
SLRD
t
XFD
N+2
N+2
IFCLK
N+2
N+3
N+3
IFCLK
t
XFD
XFD
(measured from the rising edge
N+4
N+4
IFCLK
N+3
SLRD
t
>= t
XFD
RDH
N+4
N+4
IFCLK
t
CY7C68013
N+4
OEoff
SLOE
T=3
T=4
t
FAH
Page 40 of 48
Not Driven
IFCLK
N+4