CY7C68013-56LFC Cypress Semiconductor Corp, CY7C68013-56LFC Datasheet - Page 17

• Manufacturer Part Number: CY7C68013-56LFC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C68013-56LFC

• Cpu Family: FX2LP
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 48MHz
• Interface Type: USB
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 24
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Package Type: QFN EP
• Lead Free Status / Rohs Status: Not Compliant

Table 4-1. FX2 Pin Descriptions (continued)
Document #: 38-08012 Rev. *F
TQFP
Port A
128
35
12
82
83
84
85
89
90
91
11
1
TQFP
100
100
10
67
68
69
70
71
72
73
11
SSOP
56
12
40
41
42
43
44
45
46
11
5
QFN
56
54 CLKOUT
33 PA0 or
34 PA1 or
35 PA2 or
36 PA3 or
37 PA4 or
38 PA5 or
39 PA6 or
5
4
EA
XTALIN
XTALOUT
INT0#
INT1#
SLOE
WU2
FIFOADR0
FIFOADR1
PKTEND
Name
Output
Type
Input
Input
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
O/Z
[5]
Default
12 MHz 12-, 24- or 48-MHz clock, phase locked to the 24-MHz input clock.
(PA0)
(PA1)
(PA2)
(PA3)
(PA4)
(PA5)
(PA6)
N/A
N/A
N/A
I
I
I
I
I
I
I
External Access. This pin determines where the 8051 fetches
code between addresses 0x0000 and 0x1FFF. If EA = 0 the 8051
fetches this code from its internal RAM. IF EA = 1 the 8051 fetches
this code from external memory.
Crystal Input. Connect this signal to a 24-MHz parallel-resonant,
fundamental mode crystal and load capacitor to GND.
It is also correct to drive XTALIN with an external 24 MHz square
wave derived from another clock source.
Crystal Output. Connect this signal to a 24-MHz parallel-
resonant, fundamental mode crystal and load capacitor to GND.
If an external clock is used to drive XTALIN, leave this pin open.
The 8051 defaults to 12-MHz operation. The 8051 may tri-state
this output by setting CPUCS.1 = 1.
Multiplexed pin whose function is selected by:
PORTACFG.0
PA0 is a bidirectional IO port pin.
INT0# is the active-LOW 8051 INT0 interrupt input signal, which
is either edge triggered (IT0 = 1) or level triggered (IT0 = 0).
Multiplexed pin whose function is selected by:
PORTACFG.1
PA1 is a bidirectional IO port pin.
INT1# is the active-LOW 8051 INT1 interrupt input signal, which
is either edge triggered (IT1 = 1) or level triggered (IT1 = 0).
Multiplexed pin whose function is selected by two bits:
IFCONFIG[1:0].
PA2 is a bidirectional IO port pin.
SLOE is an input-only output enable with programmable polarity
(FIFOPOLAR.4) for the slave FIFOs connected to FD[7..0] or
FD[15..0].
Multiplexed pin whose function is selected by:
WAKEUP.7 and OEA.3
PA3 is a bidirectional I/O port pin.
WU2 is an alternate source for USB Wakeup, enabled by WU2EN
bit (WAKEUP.1) and polarity set by WU2POL (WAKEUP.4). If the
8051 is in suspend and WU2EN = 1, a transition on this pin starts
up the oscillator and interrupts the 8051 to allow it to exit the
suspend mode. Asserting this pin inhibits the chip from
suspending, if WU2EN=1.
Multiplexed pin whose function is selected by:
IFCONFIG[1..0].
PA4 is a bidirectional I/O port pin.
FIFOADR0 is an input-only address select for the slave FIFOs
connected to FD[7..0] or FD[15..0].
Multiplexed pin whose function is selected by:
IFCONFIG[1..0].
PA5 is a bidirectional I/O port pin.
FIFOADR1 is an input-only address select for the slave FIFOs
connected to FD[7..0] or FD[15..0].
Multiplexed pin whose function is selected by the IFCONFIG[1:0]
bits.
PA6 is a bidirectional I/O port pin.
PKTEND is an input-only packet end with programmable polarity
(FIFOPOLAR.5) for the slave FIFOs connected to FD[7..0] or
FD[15..0].
Description
CY7C68013
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